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參數資料
| 型號： | RC32434-400BCI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDT TInterprise Integrated Communications Processor |
| 中文描述： | IDT公司TInterprise集成通信處理器 |
| 文件頁數： | 1/53頁 |
| 文件大小： | 444K |
| 代理商： | RC32434-400BCI |
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January 19, 2006
2005 Integrated Device Technology, Inc.
DSC 6214
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
Devic e Overview
The RC32434 is a member of the IDT Interprise famly of PCI
integrated communications processors. It incorporates a high perfor-
mance CPU core and a number of on-chip peripherals. The integrated
processor is designed to transfer information fromI/O modules to main
memory with mnimal CPU intervention, using a highly sophisticated
direct memory access (DMA) engine. All data transfers through the
RC32434 are achieved by writing data froman on-chip I/O peripheral to
main memory and then out to another I/O module.
Features
N
32-bit CPU Core
–
MIPS32 instruction set
–
Cache Sizes: 8KB instruction and data caches, 4-Way set
associative, cache line locking, non-blocking prefetches
–
16 dual-entry JTLB with variable page sizes
–
3-entry instruction TLB
–
3-entry data TLB
–
Max issue rate of one 32x16 multiply per clock
–
Max issue rate of one 32x32 multiply every other clock
–
CPU control with start, stop, and single stepping
–
Software breakpoints support
–
Hardware breakpoints on virtual addresses
–
ICE Interface that is compatible with v2.5 of the EJTAG Spec-
ification
N
PCI Interface
–
32-bit PCI revision 2.2 compliant
–
Supports host or satellite operation in both master and target
modes
–
Support for synchronous and asynchronous operation
–
PCI clock supports frequencies from16 MHz to 66 MHz
–
PCI arbiter in Host mode: supports 6 external masters, fixed
priority or round robin arbitration
–
I
2
O “like” PCI Messaging Unit
N
Ethernet Interface
–
10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant
–
Supports MII or RMII PHY interface
–
Supports 64 entry hash table based multicast address filtering
–
512 byte transmt and receive FIFOs
–
Supports flow control functions outlined in IEEE Std. 802.3x-
1997
N
DDR Memory Controller
–
Supports up to 256MB of DDR SDRAM
–
1 chip select supporting 4 internal DDR banks
–
Supports a 16-bit wide data port using x8 or x16 bit wide DDR
SDRAMdevices
–
Supports 64 Mb, 128 Mb, 256 Mb, 512 Mb, and 1Gb DDR
SDRAMdevices
–
Data bus multiplexing support allows interfacing to standard
DDR DIMMs and SODIMMs
–
Automatic refresh generation
Block Diagram
EJTAG
MMU
D. Cache
I. Cache
MIPS-32
CPU Core
ICE
Interrupt
Controller
3 Counter
Timers
DMA
Controller
Arbiter
DDR
(16-bit)
1 UART
(16550)
GPIO
Interface
PCI
Master/Target
Interface
Memory &
Peripheral Bus (8-bit)
Serial Channel
GPIO Pins
PCI Bus
Controller
SPI
SPI Bus
:
:
10/100
Interface
1 Ethernet
MII/RMII
IPBus
TM
PCI Arbiter
(Host Mode)
PMBus
DDR
Controllers
Memory & I/O
Controller
Bus/System
Integrity
Monitor
I
2
C
Controller
I
2
C Bus
RC32434
IDT
TM
Interprise
TM
Integrated
Communications Processor
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