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參數(shù)資料
型號(hào): RD74LVC125BFPEL
元件分類: 總線收發(fā)器
英文描述: LVC/LCX/Z SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
封裝: SOP-14
文件頁(yè)數(shù): 1/9頁(yè)
文件大小: 105K
代理商: RD74LVC125BFPEL
Rev.2.00 Dec. 10, 2004 page 1 of 8
RD74LVC125B
Quad. Bus Buffer Gates with 3-state Outputs
REJ03D0498–0200
Rev.2.00
Dec. 10, 2004
Description
The RD74LVC125B has four bus buffer gates in a 14 pin package. The device requires the three state control input
OE
to be taken high to put the output into the high impedance condition. Low voltage and high-speed operation is suitable
at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for
long time operation.
Features
V
CC = 1.65 V to 5.5 V
All inputs V
IH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs V
OUT (Max.) = 5.5 V (@VCC = 0 V or output off state)
Typical V
OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical V
OH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current
±4 mA (@VCC = 1.65 V)
±8 mA (@VCC = 2.3 V)
±12 mA (@VCC = 2.7 V)
±24 mA (@VCC = 3.0 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
Package
Abbreviation
Taping Abbreviation
(Quantity)
RD74LVC125BFPEL
SOP–14 pin (JEITA)
FP–14DAV
FP
EL (2,000 pcs/reel)
RD74LVC125BTELL
TSSOP–14 pin
TTP–14DV
T
ELL (2,000 pcs/reel)
Function Table
Inputs
OE
A
Outputs Y
H
X
Z
L
H
H:
High level
L:
Low level
X:
Immaterial
Z:
High impedance
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