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參數(shù)資料
| 型號(hào)： | RM100355WFQMLV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 鎖存器 |
| 英文描述： | 100K SERIES, LOW LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CQFP24 |
| 封裝： | CERQUAD-24 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 188K |
| 代理商： | RM100355WFQMLV |
100355
Low Power Quad Multiplexer/Latch
General Description
The 100355 contains four transparent latches, each of which
can accept and store data from two sources. When both En-
able (E
n) inputs are LOW, the data that appears at an output
is controlled by the Select (S
n) inputs, as shown in the Oper-
ating Mode table. In addition to routing data from either D
0 or
D
1, the Select inputs can force the outputs LOW for the case
where the latch is transparent (both Enables are LOW) and
can steer a HIGH signal from either D
0 or D1 to an output.
The Select inputs can be tied together for applications re-
quiring only that data be steered from either D
0 or D1.A
positive-going signal on either Enable input latches the out-
puts. A HIGH signal on the Master Reset (MR) input over-
rides all the other inputs and forces the Q outputs LOW. All
inputs have 50 k
pulldown resistors.
Features
n Greater than 40% power reduction of the 100155
n 2000V ESD protection
n Pin/function compatible with 100155
n Voltage compensated operating range = 4.2V to 5.7V
n Standard Microcircuit Drawing
(SMD) 5962-9165401
Logic Symbol
Pin Names
Description
E
1,E2
Enable Inputs (Active LOW)
S
0,S1
Select Inputs
MR
Master Reset
D
na–Dnd
Data Inputs
Q
a–Qd
Data Outputs
Q
a–Qd
Complementary Data Outputs
Connection Diagrams
DS100294-1
24-Pin DIP
DS100294-2
24-Pin Quad Cerpak
DS100294-3
August 1998
100355
Low
Power
Quad
Multiplexer/Latch
1998 National Semiconductor Corporation
DS100294
www.national.com
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