
4-1
TM
AN9824
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Copyright
Intersil Corporation 2000
SPICE Model Tutorial of the RSLIC18 AC Loop
The AC loop of the RSLIC18
refers to the voice band path
which provides full duplex
signal communication and
impedance synthesis. The
circuit operation is described here in as well as the
macromodel used to simulate the AC performance of the
device. The architecture is the same for all part numbers
available in the RSLIC18 family of ringing subscriber line
interface circuits.
The information in this document applies to all part numbers
of the RSLIC18 family: HC55180, HC55181, HC55182,
HC55183 and HC55184.
Architectural Description
The complete AC response of the device is determined by a
the dominant AC loop and a low frequency DC loop. The DC
loop provides the loop current limit function and contributes
to the AC characteristics below 400Hz. The operation of the
DC loop will not be discussed in detail, however the effects
of this loop are included in the macromodel.
Voltage Feed Current Sense
The AC loop is designed around a voltage feed current
sense architecture. The AC loop current is sensed across a
pair of low value resistors which are in series with the Tip
and Ring amplifier outputs. These sense resistors are placed
within the feedback loop of each amplifier, compensating for
voltage loss. All internal resistors use ratio relationships
providing superb matching, temperature stability and gain
accuracies.
The voltage across each resistor is measured using a
differential amplifier, referred to as the sense amplifier (SA).
The sense amplifier is configured as a dual differential
amplifier. The sense connections to the amplifier are
“flipped” resulting in addition of metallic signals (AC voice
and DC loop current) and cancellation of longitudinal
currents.
The output of the sense amplifier drives an inverting
amplifier referred to as the transmit amplifier (TA). The gain
of the transmit amplifier is set by the external component
RS, which sets the synthesized impedance for the device.
The output of the transmit amplifier provides the 4-wire
output of the device as well as the feedback required for
impedance synthesis. The feedback signal for impedance
matching is inverted with respect to the incoming voice
signal at the receive input VRX.
The receiver represents a unity gain current summing node.
The voice signal at the VRX input and the feedback signal at
the VTX output each drive internal resistors. The currents
formed by the respective voltages and resistors are summed
by a high impedance current summing junction. The sum of
the currents are mirrored and drive the inverting terminal of
the Tip and Ring amplifiers. The mirrored output of the
receiver sources Tip current and sinks Ring current,
providing the differential 2-wire output for the device.
FIGURE 1. RSLIC18 AC SIGNAL TRANSMISSION SIGNAL PATH
TIP
RING
+
-
-IN
VRX
VTX
R
R
4R
+
-
+
-
+
-
1:1
20
20
R
4R
4R
4R
R
8K
R
S
C
FB
TA
R
VFB
SA
HC5518x
R
Application Note
October 1998