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參數資料
| 型號： | RT9167A-34CS |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | LOW NOISE FIXED OUTPUT VOLTAGE 200MA/500MA LDO REGULATOR |
| 中文描述： | 低噪聲固定輸出電壓200MA/500MA LDO穩壓器 |
| 文件頁數： | 10/14頁 |
| 文件大小： | 257K |
| 代理商： | RT9167A-34CS |
RT9167/A
www.richtek-ic.com.tw
10
DS9167/A-10 July 2001
Current Limit and Thermal Protection
The RT9167 includes a current limit which monitors
and controls the pass transistor’s gate voltage limiting
the output current to 300mA Typ. (700mA Typ. for
RT9167A). Thermal-overload protection limits total
power dissipation in the RT9167/A. When the junction
temperature exceeds T
J
= +155°C, the thermal sensor
signals the shutdown logic turning off the pass
transistor and allowing the IC to cool. The thermal
sensor will turn the pass transistor on again after the
IC’s junction temperature cools by 10°C, resulting in a
pulsed output during continuous thermal-overload
conditions. Thermal-overloaded protection is designed
to protect the RT9167/A in the event of fault conditions.
Do not exceed the absolute maximum junction-
temperature rating of T
J
= +150°C for continuous
operation. The output can be shorted to ground for an
indefinite amount of time without damaging the part by
cooperation of current limit and thermal protection.
Operating Region and Power Dissipation
The maximum power dissipation of RT9167/A
depends on the thermal resistance of the case and
circuit board, the temperature difference between the
die junction and ambient air, and the rate of airflow.
The power dissipation across the device is P = I
OUT
(V
IN
- V
OUT
). The maximum power dissipation is:
PMAX = (T
J
- T
A
) /
θ
JA
where T
J
- T
A
is the temperature difference between
the RT9167/A die junction and the surrounding
environment,
θ
JA
is the thermal resistance from the
junction to the surrounding environment. The GND pin
of the RT9167/A performs the dual function of
providing an electrical connection to ground and
channeling heat away. Connect the GND pin to ground
using
a
large
pad
or
ground
plane.
Fig. 3
V
IN
V
OUT
Fig. 4
V
IN
V
OUT
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