- 您現在的位置：買賣IC網 > PDF目錄374645 > S2009 (Applied Micro Circuits Corp.) 1.6 Gbps Quad Serial Backplane Device(用于高速串行數據傳送的1.6 Gbps四串行收發器) PDF資料下載
參數資料
| 型號： | S2009 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | 1.6 Gbps Quad Serial Backplane Device(用于高速串行數據傳送的1.6 Gbps四串行收發器) |
| 中文描述： | 1.6 Gbps的四串行背板設備（用于高速串行數據傳送的1.6 Gbps的四串行收發器） |
| 文件頁數： | 1/42頁 |
| 文件大小： | 1866K |
| 代理商： | S2009 |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
1
S2009
S2009
1.6 GBPS QUAD SERIAL BACKPLANE DEVICE
February 9, 2001 / Revision C
DEVICE
SPECIFICATION
MAC
(ASIC)
S2009
QUAD
GIGABIT
ETHERNET
INTERFACE
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
TO SERIAL BACKPLANE
S2204
GE INTERFACE
SERIAL BP DRIVER
Figure 1. Typical Quad Gigabit Ethernet Application
FEATURES
CMOS Technology
Broad operating rate range (1.3 - 1.6 Gbps)
- 1.6 Gbps
- 1/2 Rate Operation
Quad Transmitter with Phase-Lock Loop (PLL)
clock synthesis from low speed reference
Quad Receiver PLL provides clock and data
recovery
Internally series terminated TTL outputs
On-chip 8B/10B line encoding and decoding for
four separate parallel 8-bit channels
32-bit parallel TTL interface with internal series
terminated outputs
Low-jitter serial PECL interface
Individual local loopback control
JTAG 1149.1 Boundary scan on low speed I/O
signals
Interfaces with coax, twinax, or fiber optics
Single +3.3 V supply, 2.65 W power dissipation
Compact 23 mm x 23 mm 208 pin
TBGA package
APPLICATIONS
Ethernet Backbones
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2009 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, serial backplanes, and proprietary point to
point links. The chip provides four separate trans-
ceivers which can be operated individually or locked
together for an aggregate data capacity of >5 Gbps.
Each bi-directional channel provides 8B/10B coding/
decoding, parallel-to-serial and serial-to-parallel con-
version, clock generation/recovery, and framing. The
on-chip transmit PLL synthesizes the high-speed
clock from a low-speed reference. The on-chip quad
receive PLL is used for clock recovery and data re-
timing on the four independent data inputs. The
transmitter and receiver each support differential
PECL-compatible I/O for copper or fiber optic com-
ponent interfaces with excellent signal integrity. Lo-
cal loopback mode allows for system diagnostics.
The chip requires a +3.3 V power supply and dissi-
pates 2.65 watts.
Figure 1 shows the S2009 and S2204 in a Gigabit
Ethernet application. Figure 2 combines the S2009
with a crosspoint switch to demonstrate a serial
backplane application. Figure 3 is the input/output
diagram. Figures 4 and 5 show the transmit and
receive block diagrams, respectively.
相關PDF資料 |
PDF描述 |
|---|---|
| S2012D | SCRs (1 A to 70 A) |
| S2012D | SCRs |
| S2012R | SCRs |
| S2012V | SCRs |
| S2015L | SCRs 1-70 AMPS NON-SENSITIVE GATE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| S2009TB | 制造商:AppliedMicro 功能描述: 制造商:AMC 功能描述: |
| S200-A-1325 | 制造商:Selco Products 功能描述:ADJUSTABLE TEMP CONTROL, 75-425 DEG |
| S-200C R RD | 制造商:CSYS 功能描述: |
| S200-F-1 | 制造商:Selco Products 功能描述:ADJUSTABLE TEMP CONTROL, 75-575 DEG |
| S200K25SL0N63L6R | 功能描述:瓷片電容器 .25LS 20PF 1KV 10% RoHS:否 制造商:Vishay/Cera-Mite 電容:0.01 uF 容差:20 % 電壓額定值:3 kV 工作溫度范圍:- 25 C to + 105 C 損耗因數 DF: 端接類型:Radial 產品:High Voltage Ceramic Disc Capacitors |
發布緊急采購，3分鐘左右您將得到回復。