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參數資料
| 型號： | S2028A |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | 32-BIT, DSP-CROSSBAR SWITCH, PQFP224 |
| 封裝： | LDCC-224 |
| 文件頁數： | 1/20頁 |
| 文件大小： | 147K |
| 代理商： | S2028A |
1
33 x 32 1.25 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2028
July 2, 1999 / Revision C
Figure 1. Functional Block Diagram
FEATURES
33 x 32 differential crosspoint switch
Full broadcast switching capability
Differential 10K PECL data path
Configurable differential output driver
controls
Up to 1.25 Gbit/s NRZ data rate
TTL configuration controls
Reconfigurable without disturbing
operation
Single cycle broadcast configuration
High-speed multicast and fast unicast
configuration (100 MHz)
“Break” feature to disable previous
multicast configuration
224-pin LDCC package
APPLICATIONS
Internet Switches
Datacom or telecom switching
Digital demultiplexing
Microwave or fiber-optic data distribution
High-speed automatic test equipment
Digital video
33 x 32 1.25 GBIT/S DIFFERENTIAL CROSSPOINT SWITCH
S2028
DEVICE
SPECIFICATION
GENERAL DESCRIPTION
The S2028 is a very high-speed 33 x 32 differential
crosspoint switch with fast multicast and broadcast
capabilities. It consists of 32 differential PECL input
signal pairs that can be connected to any or all of its
32 differential PECL output signal pairs. In addition,
the differential output drivers can be individually con-
figured to gate in an additional broadcast channel.
This channel can be used as a default advertise
channel, or to supply a signal such as a clock to
simplify interface design.
Along with a single cycle reconfiguration of the entire
33 x 32 crosspoint switch, the S2028 features single
cycle broadcast and fast two cycle multicast configu-
ration. A “break” feature allows fast unicast or
multicast disable of the previous configuration.
The S2028 contains a unique memory map, which
provides full support of the broadcast, multicast, and
unicast modes.
The differential 10K PECL logic data path makes the
part ideal for high-speed applications. The differential
nature of the data path is retained throughout the
crosspoint structure, to minimize data distortion and to
handle NRZ data rates up to 1.25 gigabits per second.
PECL
Diff.
Input
Buffers
PECL
Diff.
Output
Buffers
33 x 32
Differential
Crosspoint
66
64
DIN00P
DIN31P
DOUT00P
DOUT31P
Active Configuration Latch
192
16
32 x 6
Configuration
Register File
192
RESETN
CONFIGN
CRFDATA
LOADN
CRFADDR
OADDR/OUTPUT MASK
DOUT00N
DOUT31N
DIN00N
DIN31N
ADVERTISEP
ADVERTISEN
1
BROADCAST
1
MULTICAST
1
BREAK
1
BANKSEL
5
IADDR
BROADCAST
MULTICAST
BREAK
BANKSEL
IADDR
1
ADVERT
10
1
WRITE
CSN
1
CHIP SELECT
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