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參數(shù)資料
| 型號： | S2060B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | GIGABIT ETHERNET TRANSCEIVER |
| 中文描述： | 千兆以太網(wǎng)收發(fā)器 |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 693K |
| 代理商： | S2060B |
1
S2060
S2060
GIGABIT ETHERNET TRANSCEIVER
March 7, 2001 / Revision H
DEVICE
SPECIFICATION
FEATURES
Operating rate
1250 MHz (Gigabit Ethernet) line rates
Half and full VCO output rates
Functionally compliant IEEE 802.3z Gigabit
Ethernet standard
Transmitter incorporating Phase-Locked Loop
(PLL) clock synthesis from low speed reference
Receiver PLL provides clock and data recovery
10-bit parallel TTL compatible interface
Low-jitter serial LVPECL compatible interface
Local loopback
Single +3.3 V supply, 620 mW power dissipation
64 PQFP or TQFP package
Continuous downstream clocking from receiver
Drives 30 m of Twinax cable directly
APPLICATIONS
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2060 transmitter and receiver chip facilitates
high speed serial transmission of data over fiber op-
tic, coax, or twinax interfaces. The device conforms
to the requirements of the IEEE 802.3z Gigabit
Ethernet specification, and runs at 1250.0 Mbps data
rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-par-
allel conversion, clock generation/recovery, and
framing for block encoded data. The on-chip transmit
PLL synthesizes the high-speed clock from a low-
speed reference. The on-chip receive PLL performs
clock recovery and data re-timing on the serial bit
stream. The transmitter and receiver each support
differential LVPECL compatible I/O for copper or fi-
ber optic component interfaces with excellent signal
integrity. Local loopback mode allows for system di-
agnostics. The chip requires a +3.3 V power supply
and dissipates typically 620 mW.
The S2060 can be used for a variety of applications
including Gigabit Ethernet, serial backplanes, and
proprietary point-to-point links. Figure 1 shows a
typical configuration incorporating the chip.
Figure 1. System Block Diagram
S2060
Gigabit
Ethernet
Controller
Optical
Tx
Optical
Rx
Optical
Tx
Optical
Rx
S2060
Gigabit
Ethernet
Controller
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S2060C | GIGABIT ETHERNET TRANSCEIVER |
| S2060D | GIGABIT ETHERNET TRANSCEIVER |
| S2060 | GigaBit Ethernet Transceiver(帶并/串和串/并轉(zhuǎn)換，時鐘發(fā)生/恢復(fù)功能的千兆位以太網(wǎng)收發(fā)器) |
| S2060 | Silicon Power Rectifier |
| S2061 | Serial Backplane Transceiver(用于高速串行數(shù)據(jù)傳送的收發(fā)器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S2060C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:GIGABIT ETHERNET TRANSCEIVER |
| S2060CCR | 制造商:Intel 功能描述: |
| S2060D | 制造商:RCA 功能描述: 制造商:AMC 功能描述: |
| S-2060-GX | 制造商:Eagle Aspen 功能描述:SATELLITE MULTISWITCH2X16 RACK MOUNT 950~2150MHZ |
| S2060QSC | 制造商:AppliedMicro 功能描述:GIGABIT ETHERNET/FIBRE CHANNEL TRANSCEIVER 制造商:AMCC 功能描述:1250MBITS/S GBE TRANSCEIVER EOL280308 |
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