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參數(shù)資料
| 型號： | S3029 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Clock Synthesis and Recovery Unit(數(shù)據(jù)傳送速率155 MBit/S的時鐘合成和恢復單元) |
| 中文描述： | 時鐘合成及回收機（數(shù)據(jù)傳送速率155兆比特/秒的時鐘合成和恢復單元） |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 65K |
| 代理商： | S3029 |
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 (619) 450-9333
1
S3029 TO WAC-413 AND 3.3V OPTICAL MODULE APPLICATIONS NOTE
S3029 TO WAC-413 AND 3.3V OPTICAL MODULE APPLICATIONS NOTE
INTRODUCTION
Connecting AMCC’s latest low power 3.3V SONET/SDH STS-3/STM-1 Quad Clock Recovery Unit to the Quad
IGT WAC-413 UNI Processor and to 3.3V 1x9 F/O optical modules provides the Physical Media Dependent
(PMD) layer for SONET/SDH data transfer. The S3029 is capable of receiving four STS-3/STM-1 scrambled
NRZ signals and recovering the clock from the data. The S3029 extracts the data and the clock from the receive
data stream and provides the data, the receive clock, and the transmit clock to the WAC-413. The S3029 also
supplies the WAC-413 with a line fault indicator signal which will be supplied to the processor in the absence or
in the presence of an unreliable signal at the input of the optical module. The block diagram in Figure 1-1 depicts
the implementation of an AMCC S3029 used in conjunction with a WAC-413 and a 1x9 F/O receiver to
implement a true four channel 3.3V STS-1, STS-3/OC-3 or STM-1 solution in two chips (not including optics).
Each transmit/receive pair requires one optics module for a total of four modules.
Signal Connect Description
Figure 1 shows the implementation of this solution.
1.
The Transmit Section Serial Data (*TS_SERDATA+/-) output bits (3 to 0) of the WAC-413 are connected to the
transmit data (TxD/TxDn*) input bits (3 to 0) of the four optical modules. The optical modules in the transmit path
convert the electrical data to optical data format. These interfaces are 3.3V PECL.
2.
The Transmit Section Serial Clock (*TS_SER_CLK+/-) input bits (3 to 0) of the WAC-413 are connected to the
Transmit Clock Out (TXCLKOP/N) output bit of the S3029. These interfaces are 3.3V PECL.
3.
The Receive Section Serial Data (*RS_SER_DATA+/-) input bits (3 to 0) of the WAC-413 are connected to the
Serial Data Out (SERDATOP/N*) output bits (3 to 0) of the S3029. These interfaces are 3.3V PECL
4.
The Receive Section Serial Clock (*RS_SER_CLK+/-) input bits (3 to 0) of the WAC-413 are connected to the Serial
Clock Out (SERCLKOP/N*) output bits (3 to 0) of the S3029. These interfaces are 3.3V PECL.
5.
The Receive Lock (*RX_LOCK) input bits (3 to 0) of the WAC-413 are connected to the Lock Detect (LOCKDET*)
output bits (3 to 0) of the S3029. These interfaces are 3.3V TTL. A high level indicates that the Phase Lock Loop
(PLL) is locked. A low level is the line fault indicator signal.
6.
The Reference Clock (REFCLKP/N) input into the S3029 is a 3.3V PECL interface that is connected to the 19.44
MHz PECL clock source. The Reference Select (REFSEL) input of the S3029 must be a TTL low for this reference
choice.
7.
The Signal Detect (SD*) input bits (3 to 0) into the S3029 (single ended 10K ECL inputs) is connected to the RX
SD* output bits (3 to 0) of the optical modules. This signal when Low, indicates loss of received optical power,
therefore, the data on the Serial Data In (SERDATIP/N) pins will be internally forced to a constant zero, LOCKDET*
forced low, and the PLL forced to lock to the REFCLKP/N input.
8.
The Serial Data Input (SERDATIP/N*) bits (3 to 0) of the S3029 are connected to the RxD/RxDn* output bits (3
to 0) of the Optical Module. The optical modules in the receive path convert the optical data to electrical data format.
These interfaces are 3.3V PECL.
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