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參數資料
| 型號： | S3057 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Multi-Rate SONET/SDH/ATM Transceiver(帶片上鎖相環的多速率SONET/SDH/ATM收發器) |
| 中文描述： | 多速率SONET / SDH / ATM的收發器（帶片上鎖相環的多速率的SONET / SDH / ATM的收發器） |
| 文件頁數： | 1/26頁 |
| 文件大小： | 238K |
| 代理商： | S3057 |
1
S3057
S3057
MULTIRATE (OC-48/24/12/3/GBE) SONET/SDH/ATM TRANSCEIVER
October 31, 2000 / Revision E
DEVICE
SPECIFICATION
FEATURES
SiGe BiCMOS technology
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLL for clock
generation
Supports OC-48 (2488.32 Mbps),
OC-24 (1244.16 Mbps),
Gigabit Ethernet (1250 Mbps),
OC-12 (622.08 Mbps),
OC-3 (155.52 Mbps)
Reference frequency of 155.52 MHz
Interface to LVPECL and TTL logic
16-Bit single-ended LVPECL data path
Compact 156 TBGA package
Diagnostic loopback mode
Supports line timing
Lock Detect
Signal detect input
Low jitter LVPECL interface
Internal FIFO to decouple transmit clocks
Single 3.3V supply
Typical power 1.5 W
APPLICATIONS
Wavelength Division Multiplexing (WDM)
equipment
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
Figure 1. System Block Diagram
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
GENERAL DESCRIPTION
The S3057 SONET/SDH transceiver chip is a fully
integrated multirate serialization/deserialization SO-
NET OC-48 (2488.32 Mbps), OC-24 (1244.16
Mbps), Gigabit Ethernet (1250 Mbps), OC-12
(622.08 Mbps) and OC-3 (155.52 Mbps) interface
device. The chip performs all necessary serial-to-
parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission stan-
dards. The device is suitable for SONET-based
WDM applications. Figure 1 shows a typical network
application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3057
transceiver chip allowing the use of a slower external
transmit clock reference. The chip can be used with
a 155.52 MHz reference clock in support of existing
system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3057 is pack-
aged in a 156 TBGA, offering designers a small
package outline.
S3056
Clock
Recovery
Unit
S3052
Receive
S3052
Transmit
S3057
Transmit
Serialization
S3057
Receive
Deserialization
S3056
Clock
Recovery
Unit
S3052
Receive
S3052
Transmit
S3057
Transmit
Serialization
S3057
Receive
Deserialization
2.488 Gbps
2.488 Gbps
155.52 Mbps
155.52 Mbps
2.488 Gbps
2.488 Gbps
PERFORMANCE MONITOR
PERFORMANCE MONITOR
E/O
O/E
OPTICAL FIBER
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相關代理商/技術參數 |
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|---|---|
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