
1
S3076
S3076
BiCMOS PECL CLOCK GENERATOR
October 23, 2000 / Revision A
DEVICE
SPECIFICATION
FEATURES
SiGe BiCMOS technology
Complies with Bellcore and ITU-T specifica-
tions for jitter tolerance, jitter transfer and
jitter generation
On-chip high frequency PLL with internal
loop filter for clock recovery
Supports clock recovery for:
OC-48 (2488.32 Mbps) (with FEC)
Fibre Channel (2125 Mbps) (with FEC)
OC-24 (1244.16 Mbps) (with FEC)
Gigabit Ethernet (1250 Mbps) (with FEC)
Fibre Channel (1062.5 Mbps) (with FEC)
OC-12 (622.08 Mbps) (with FEC)
OC-3 (155.52 Mbps)
(with FEC)
NRZ data
Selectable reference frequencies
19.44 MHz or 155.52 MHz
(or equivalent Fibre Channel/
Gigabit Ethernet frequencies)
Lock detect—monitors frequency of
incoming data
Low-jitter serial interface
+3.3 V supply
Compact 48 pin TQFP TEP package
Typical power 620 mW
Available in Die form also
GENERAL DESCRIPTION
The function of the S3076 clock recovery unit is to
derive high speed timing signals for SONET/SDH-
based equipment. The S3076 is implemented using
AMCC’s proven Phase Locked Loop (PLL) technology.
Figure 1 shows a typical network application.
The S3076 receives an OC-48, OC-24, OC-12, OC-3,
Fibre Channel or Gigabit Ethernet scrambled NRZ sig-
nal with FEC capability up to 8 bytes per 255-byte
block and recovers the clock from the data. The chip
outputs a differential bit clock and retimed data.
The S3076 utilizes an on-chip PLL which consists
of a phase detector, a loop filter, and a Voltage
Controlled Oscillator (VCO). The phase detector
compares the phase relationship between the VCO
output and the serial data input. A loop filter con-
verts the phase detector output into a smooth DC
voltage, and the DC voltage is input to the VCO
whose frequency is varied by this voltage. A block
diagram is shown in Figure 2.
Figure 1. System Block Diagram
N
P
N
P
S3057
S3057
OTX
ORX
OTX
ORX
16
16
16
16
S3076
S3076