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參數(shù)資料
| 型號： | S4804CBI41 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, CBGA624 |
| 封裝： | CERAMIC, BGA-624 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 49K |
| 代理商： | S4804CBI41 |
Features
S4804CBI Block Diagram
RHINE
OC-48 / 4xOC-12 / 16xOC-3 SONET/SDH FRAMER AND POS/ATM MAPPER
Part Number - S4804CBI41
Product Brief Version 2.0 - January 2002
PRODUCT BRIEF
AMCC
Production Release Information
- The information con-
tained in this document is about a product in its fully tested
and characterized phase. All features described herein are
supported. Contact AMCC for updates to this document and
the latest product status.
Provides a SONET/SDH STS-48/STM-16, 4 STS-12/STM-
4, or 16 STS-3/STM-1 line interfaces.
STS-48/STM-16 data stream supports a single STS-48c/
AU-4-16c, or any valid combination of STS-12c/AU-4-4c
and/or STS-3c/AU-4 SONET/SDH payloads.
Each STS-12/STM-4 data stream supports a single STS-
12c/AU-4-4c or 4 STS-3c/AU-4 SONET/SDH payloads.
Each STS-3/STM-1 data stream supports a single
STS-3c/AU-4 SONET/SDH payload.
Supports mixed STS-3 / STS-12 line rates
Provides full-duplex mapping of ATM cells or packets in
each payload tributary.
Supports termination of mixed ATM and POS tributaries.
Terminates/generates SONET/SDH section, line, and path
layers with transport/section E1, E2, F1, and DCC over-
head interfaces in both transmit and receive directions.
APS port to support protection-switching configurations
between two RHINE devices.
16-bit, bus interface at 155 MHz for STS-48/STM-16 mode,
or serial interfaces operating at 622/155 MHz for STS-12/3
(STM-4/1) modes on the line side.
32-bit, parallel interface (FlexBus-3
TM
) operating at 100
MHz on the system side.
.25 micron, 2.5V core, and 3.3V tolerant I/O.
Packaged in a 624 Pin CBGA.
The S4804 is a highly-integrated VLSI device that provides
full-duplex mapping of packets or ATM cells to SONET/SDH
payloads. It provides support for both uni-directional and
bi-directional rings.
The S4804 provides full section, line, and path overhead
processing, and supports framing, scrambling/descrambling,
alarm signal insertion/detection, and bit-interleaved parity
(B1/B2/B3) processing.
The S4804 is SONET/SDH standards compliant with Bellcore
GR-253, ITU G.707, ITU-T 432.1, ANSI T1.105 -1995, and
IETF RFCs 1619/1661/1662/2615.
A general purpose 8-bit or 16-bit microprocessor interface is
provided for control and monitoring. The interface supports
both Intel
TM
and Motorola
TM
type microprocessors, and is
capable of operating in either an interrupt-driven or
polled-mode configuration. In addition, a standard 5 signal
IEEE 1149.1 JTAG Test Port is provided for Boundary Scan
test purposes.
Applications
ATM switches
Packet over SONET Routers and Switches
SONET/SDH Add Drop Multiplexers, Terminal
Multiplexers, and Digital Cross Connects
Test equipment
U
T
TX_SYS_DAT[31:0]
TX_ADR[4:0]
TX_CLK[1:4]
TX_PRTY[1:4]
TX_ENB[1:4]
TX_SOC/P[1:4]
TX_CLAV_PDA[1:4]
TX_CLK_OUT[1:4]
RX_SYS_DAT[31:0]
RX_ADR[4:0]
RX_CLK[1:4]
RX_PRTY[1:4]
RX_ENB[1:4]
RX_SOC/P[1:4]
RX_CLAV_PDA[1:4]
RX_DV[1:4]
RX_LBYTE[1:0]
RX_EOP[1:4]
RX_ERR[1:4]
RX_CLK_OUT[1:4}
MON.
TOH EXTRACT
TOH
MON.
RX
FRAMER
L
TX
FRAMER
TOH INSERT
SPE/VC
GEN.
T
T
T
R
R
R
TX_EOP[1:4]
TX_ERR[1:4]
D
A
C
R
W
R
B
I
MICROPROCESSOR I/F
JTAG PORT
GPIO/LED REG
T
T
T
T
T
G
TX_DATA[15:0]
TX_SONETCLK_IN
TX_FRAME_IN
RX_DATA[15:0]
RX_SONETCLK[1:16]
R
R
A
T
RX_LOSEXT[1:16]
RX
FIFO
x16
HDLC
CNTRS
x16
TX
x16
x16
x16
x16
x16
x16
x16
TX_LBYTE[1:0]
TX ATM/HDLC
PROC w/
(X
43
+ 1)
SCRMBL
x16
RX ATM/HDLC
PROC w/
(X
43
+ 1)DeSCRMBL
x16
U
TX_SONETCLK_OUT_155_622
A
A
A
A
TX_SONETCLK_OUT_155
RX_REF_CLK_OUT
Ptr
Proc
Ptr
Intrp
x16
S
R
T
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| S4805 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:SONET/SDH/ATM OC-48 Transceiver With CDR |
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