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參數資料
| 型號： | S5920 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | 32-Bit PCI Bus Target Interface(32位PCI總線目標接口) |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 139K |
| 代理商： | S5920 |
6290 Sequence Drive, San Diego, California 92121-4358
800-755-2622 Fax: 619-450-9885
http://www.amcc.com
S5920
32-Bit PCI Bus Target Interface
February 12, 1997 Revised October 1998
F
EATURES
PCI 2.2 Compliant Target/Slave Device
Full 132 Mbytes/sec Transfer Rate
PCI Bus Operation DC to 33 Mhz
Add-On Bus 8 MHz to 40 Mhz
Programmable Prefetch and Wait States
8/16/32 Bit Add-On User Bus
Four Definable Pass-Thru Regions
32 Byte Burstable PCI Bus FIFO
Active/Passive Add-On Bus Operation
Mail Box Registers w/Byte Level Status
Direct Mail Box Data Strobe/Interrupt Pin
Mail Box Read/Write Interrupts
Direct PCI & Add-On Interrupt Pins
S5933 PCI Target Mode Replacement
S5933 Software Compatible
Plug-N-Play Compatible
Two Wire Serial Bus nvRAM Support
Optional External BIOS
160 Pin PQFP
A
PPLICATIONS
ISA to PCI Local Bus Conversions
I/O Communications Ports
High Speed Data Output
General Purpose PCI Interfacing
Data Communications
Memory Interfaces
Data Acquisition
Data Encryption/Decryption
D
ESCRIPTION
The AMCC S5920 was developed to provide the designer with a single multi-function device offering a flexible and
easy means to connect applications to the PCI Local Bus. Designers connecting to the PCI Local Bus through the S5920
eliminate the necessity to understand complex PCI Bus timing requirements and the time consuming task of assuring
PCI specification compliance. The S5920’s design incorporates years of design experience and system knowledge
achieved through the popular S5933 PCI Matchmaker device.
The S5920 converts complex PCI bus signals into an easy-to-use 8-, 16- or 32-bit user bus referred to as the Add-On
Local Bus. The S5920 Add-On signal pins, shown in Figure 2, provide the designer with a much simpler bus structure
in which to interface I/O, memory or data acquisition applications and to port existent ISA-based designs over to the
PCI Bus. The bus can be operated either synchronously or asynchronously to the PCI Local Bus with user definable
clock speeds from 8 to 40 MHz.
Since the S5920 is a PCI ‘Target’ or ‘Slave’ device only, its cost is significantly less than PCI Bus Master solutions
making it ideal for low cost applications. The S5920 is compliant with the PCI Local Bus Specification Revision 2.2. It
is capable of 132 Mbytes/sec data transfer rates and supports both burst and single DWORD data transfers. The S5920
logic core is powered from a single 5 volt supply and utilizes advanced AMCC technology to achieve low system power
consumption at clock speeds to 33 MHz. The S5920 block diagram is shown in Figure 1.
The S5920’s superior feature set offers the designer multiple hardware and software design options for higher perfor-
mance. Up to four Host bus memory or I/O space definable blocks, referred to as Pass-Thru regions, may be imple-
mented providing multiple data channels. Data transfers via a Pass-Thru data channel can be performed through a single
buffered to the application or through burstable FIFOs. Added read prefetch and programmable FIFO wait state features
allow the user to fine tune system performance. The Pass-Thru data channels also supports an ‘active or passive’ mode
bus interface. Passive mode requires the designer to transfer data by externally driving data onto the Add-On Bus.
Active mode minimizes design components by enabling internal logic to drive or acquire the Add-On Bus for reading or
writing data independently. Active mode also supports programmable wait state generation for slower Add-On designs.
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