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參數(shù)資料
| 型號： | SB80L186EC-13 |
| 元件分類： | 16位微控制器 |
| 英文描述： | 16-Bit Microprocessor |
| 中文描述： | 16位微處理器 |
| 文件頁數(shù)： | 32/57頁 |
| 文件大小： | 585K |
| 代理商： | SB80L186EC-13 |
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80C186EC/188EC, 80L186EC/188EC
AC SPECIFICATIONS
AC CharacteristicsD80C186EC-20/80C186EC-13
Symbol
Parameter
Min
Max
Min
Max
Unit
Notes
INPUT CLOCK
20 MHz
13 MHz
TF
TC
TCH
TCL
TCR
TCF
CLKIN Frequency
CLKIN Period
CLKIN High Time
CLKIN Low Time
CLKIN Rise Time
CLKIN Fall Time
0
40
%
%
%
10
10
0
26
%
%
%
10
10
MHz
ns
ns
ns
ns
ns
1
1
25
10
10
1
1
38.5
12
12
1
1
1, 2
1, 2
1, 3
1, 3
OUTPUT CLOCK
T
CD
T
T
PH
T
PL
T
PR
T
PF
OUTPUT DELAYS
CLKIN to CLKOUT Delay
CLKOUT Period
CLKOUT High Time
CLKOUT Low Time
CLKOUT Rise Time
CLKOUT Fall Time
0
17
0
23
ns
ns
ns
ns
ns
ns
1, 4
1
1
1
1, 5
1, 5
2
*
TC
2
*
TC
(T/2)
b
5 (T/2)
a
5 (T/2)
b
5 (T/2)
a
5
(T/2)
b
5 (T/2)
a
5 (T/2)
b
5 (T/2)
a
5
1
6
1
6
1
1
6
6
T
CHOV1
ALE, S2:0, DEN, DT/R,
BHE (RFSH), LOCK, A19:16
3
20
3
25
ns
1, 4, 6, 7
T
CHOV2
GCS7:0, LCS, UCS,
RD, WR, NCS, WDTOUT
3
23
3
30
ns
1, 4, 6, 8
T
CLOV1
BHE (RFSH), DEN, LOCK, RESOUT,
HLDA, T0OUT, T1OUT
3
20
3
25
ns
1, 4, 6
T
CLOV2
RD, WR, GSC7:0, LCS, UCS, AD15:0
(AD7:0, A15:8), NCS, INTA, S2:0, A19:16
3
23
3
30
ns
1, 4, 6
T
CHOF
RD, WR, BHE (RFSH), DT/R, LOCK,
S2:0, A19:16
0
25
0
30
ns
1
T
CLOF
INPUT REQUIREMENTS
DEN, AD15:0 (AD7:0, A15:8)
0
25
0
30
ns
1
T
CHIS
TEST, NMI, T1IN, T0IN, READY,
CTS1:0, BCLK1:0, P3.4, P3.5
10
10
ns
1, 9
T
CHIH
TEST, NMI, T1IN, T0IN, READY,
CTS1:0, BCLK1:0, P3.4, P3.5
3
3
ns
1, 9
T
CLIS
T
CLIH
T
CLIS
T
CLIH
AD15:0 (AD7:0), READY
10
10
ns
1, 10
AD15:0 (AD7:0), READY
3
3
ns
1, 10
HOLD, RESIN, PEREQ, ERROR, DRQ3:0
10
10
ns
1, 9
HOLD, RESIN, REREQ, ERROR, DRQ3:0
3
3
ns
1, 9
NOTES:
1. See
AC Timing Waveforms
, for waveforms and definition.
2. Measure at V
IH
for high time, V
IL
for low time.
3. Only required to guarantee I
CC
. Maximum limits are bounded by T
C
, T
CH
and T
CL
.
4. Specified for a 50 pF load, see Figure 14 for capacitive derating information.
5. Specified for a 50 pF load, see Figure 15 for rise and fall times outside 50 pF.
6. See Figure 15 for rise and fall times.
7. T
CHOV1
applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.
8. T
CHOV2
applies to RD and WR only after a HOLD release.
9. Setup and Hold are required to guarantee recognition.
10. Setup and Hold are required for proper operation.
32
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| SB80L188EC13 | MICROPROCESSOR|16-BIT|CMOS|QFP|100PIN|PLASTIC |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SB80L186EC16 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS |
| SB80L186EC20 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS |
| SB80L186EC25 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS |
| SB80L188EA-13 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor |
| SB80L188EB13 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS |
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