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參數資料
型號: SC16C752IB48,128
廠商: NXP Semiconductors
文件頁數: 1/47頁
文件大小: 0K
描述: IC DUAL UART 64BYTE 48LQFP
標準包裝: 1
通道數: 2,DUART
FIFO's: 64 字節
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 標準包裝
其它名稱: 568-5955-6
SC16C752
Dual UART with 64-byte FIFO
Rev. 04 — 20 June 2003
Product data
1.
Description
The SC16C752 is a dual universal asynchronous receiver/transmitter (UART) with
64-byte FIFOs, automatic hardware/software ow control, and data rates up to
5 Mbits/s (3.3 V and 5 V). The SC16C752 offers enhanced features. It has a
transmission control register (TCR) that stores receiver FIFO threshold levels to
start/stop transmission during hardware and software ow control. With the FIFO
RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one
access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user
requirements. An internal loop-back capability allows on-board diagnostics.
The UART transmits data, sent to it over the peripheral 8-bit bus, on the TX signal and
receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or
8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be
programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can
transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect
break, idle, or framing errors, FIFO overow, and parity errors. The transmitter can
detect FIFO underow. The UART also contains a software interface for modem
control operations, and has software ow control and hardware ow control
capabilities.
The SC16C752 is available in a plastic LQFP48 package.
2.
Features
s Pin compatible with SC16C2550 with additional enhancements
s Up to 5 Mbits/s baud rate (at 3.3 V and 5 V; at 2.5 V maximum baud rate is
3 Mbits/s)
s 64-byte transmit FIFO
s 64-byte receive FIFO with error ags
s Programmable and selectable transmit and receive FIFO trigger levels for DMA
and interrupt generation
s Software/hardware ow control
x Programmable Xon/Xoff characters
x Programmable auto-RTS and auto-CTS
s Optional data ow resume by Xon any character
s DMA signalling capability for both received and transmitted data
s Supports 5 V, 3.3 V and 2.5 V operation
s Software selectable baud rate generator
s Prescaler provides additional divide-by-4 function
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