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參數資料
| 型號： | SCAN18541TSSC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Non-Inverting Line Driver with 3-STATE Outputs |
| 中文描述： | SCAN/JTAG/3J SERIES, DUAL 9-BIT BOUNDARY SCAN DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 90K |
| 代理商： | SCAN18541TSSC |
2000 Fairchild Semiconductor Corporation
DS010965
www.fairchildsemi.com
October 1991
Revised April 2000
S
SCAN18541T
Non-Inverting Line Driver with 3-STATE Outputs
General Description
The SCAN18541T is a high speed, low-power line driver
featuring separate data inputs organized into dual 9-bit
bytes with byte-oriented paired output enable control sig-
nals. This device is compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture with the
incorporation of the defined boundary-scan test logic and
test access port consisting of Test Data Input (TDI), Test
Data Out (TDO), Test Mode Select (TMS), and Test Clock
(TCK).
Features
I
IEEE 1149.1 (JTAG) Compliant
I
Dual output enable signals per byte
I
3-STATE outputs for bus-oriented applications
I
9-bit data busses for parity applications
I
Reduced-swing outputs source 32 mA/sink 64 mA
I
Guaranteed to drive 50
transmission line to TTL input
levels of 0.8V and 2.0V
I
TTL compatible inputs
I
25 mil pitch SSOP (Shrink Small Outline Package)
I
Includes CLAMP and HIGHZ instructions
I
Member of Fairchild’s SCAN Products
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter
“
X
”
to the ordering code.
Connection Diagram
Pin Names
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Order Number
SCAN18541TSSC
Package Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Pin Names
AI
(0
–
8)
BI
(0
–
8)
AOE
1
, AOE
2
BOE
1
, BOE
2
AO
(0
–
8)
AO
(0
–
8)
Description
Input Pins, A Side
Input Pins, B Side
3-STATE Output Enable Input Pins,
3-STATE Output Enable Input Pins,
Output Pins, A Side
Output Pins, B Side
A Side
B Side
Inputs
AO
(0–8)
AOE
1
L
H
X
L
AOE
2
L
X
H
L
AI
(0–8)
H
X
X
L
H
Z
Z
L
Inputs
BO
(0–8)
BOE
1
L
H
X
L
BOE
2
L
X
H
L
BI
(0–8)
H
X
X
L
H
Z
Z
L
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