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參數資料
| 型號： | SCAN921025SLC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| 中文描述： | LINE DRIVER, PBGA49 |
| 封裝： | FBGA-49 |
| 文件頁數： | 1/21頁 |
| 文件大小： | 474K |
| 代理商： | SCAN921025SLC |
SCAN921025 and SCAN921226
30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer
with IEEE 1149.1 (JTAG) and at-speed BIST
General Description
The
SCAN921025
transforms
a
10-bit
wide
parallel
LVCMOS/LVTTL data bus into a single high speed Bus
LVDS serial data stream with embedded clock. The
SCAN921226 receives the Bus LVDS serial data stream and
transforms it back into a 10-bit wide parallel data bus and
recovers parallel clock.
Both devices are compliant with IEEE 1149.1 Standard for
Boundary Scan Test. IEEE 1149.1 features provide the de-
sign or test engineer access via a standard Test Access Port
(TAP) to the backplane or cable interconnects and the ability
to verify differential signal integrity. The pair of devices also
features an at-speed BIST mode which allows the intercon-
nects between the Serializer and Deserializer to be verified
at-speed.
The SCAN921025 transmits data over backplanes or cable.
The single differential pair data path makes PCB design
easier. In addition, the reduced cable, PCB trace count, and
connector size tremendously reduce cost. Since one output
transmits clock and data bits serially, it eliminates clock-to-
data and data-to-data skew. The powerdown pin saves
power by reducing supply current when not using either
device. Upon power up of the Serializer, you can choose to
activate synchronization mode or allow the Deserializer to
use the synchronization-to-random-data feature. By using
the synchronization mode, the Deserializer will establish lock
to a signal within specified lock times. In addition, the em-
bedded clock guarantees a transition on the bus every 12-bit
cycle. This eliminates transmission errors due to charged
cable
conditions.
Furthermore,
SCAN921025 output pins into TRI-STATE to achieve a high
impedance state. The PLL can lock to frequencies between
30 MHz and 80 MHz.
you
may
put
the
Features
n
IEEE 1149.1 (JTAG) Compliant and At-Speed BIST test
mode.
n
Clock recovery from PLL lock to random data patterns.
n
Guaranteed transition every data transfer cycle
n
Chipset (Tx + Rx) power consumption
<
600 mW (typ)
@
80 MHz
n
Single differential pair eliminates multi-channel skew
n
800 Mbps serial Bus LVDS data rate (at 80 MHz clock)
n
10-bit parallel interface for 1 byte data plus 2 control bits
n
Synchronization mode and LOCK indicator
n
Programmable edge trigger on clock
n
High impedance on receiver inputs when power is off
n
Bus LVDS serial output rated for 27
load
n
Small 49-lead BGA package
Block Diagrams
DS200248-1
December 2001
S
(
2001 National Semiconductor Corporation
DS200248
www.national.com
相關PDF資料 |
PDF描述 |
|---|---|
| SCAN921226SLC | 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| SCAN921260 | X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| SCAN921260UJB | X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| SCAN921260UJBX | X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| SCAN921821 | Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1(JTAG), and At-Speed BIST |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SCAN921025SLC/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數量:4 接收機數量:4 數據速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN9212224SLC/NOPB | 制造商:Texas Instruments 功能描述: |
| SCAN921224 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:20-66 MHz 10 Bit Bus LVDS Serializer and Deserializer |
| SCAN9212245LC | 制造商:Texas Instruments 功能描述: |
| SCAN921224SLC | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數量:4 接收機數量:4 數據速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
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