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參數資料
| 型號： | SCE5786 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 顯示用LED |
| 英文描述： | 5X7 DOT MATRIX DISPLAY, RED, 4.57 mm |
| 封裝： | PLASTIC, DIP-26 |
| 文件頁數： | 5/14頁 |
| 文件大小： | 208K |
| 代理商： | SCE5786 |
2001 OSRAM Opto Semiconductors Inc. San Jose, CA
SCE5780/1/2/3/4/5/6
www.inneon.com/opto 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG Regensburg, Germany
www.osram-os.com +49-941-202-7178
13
August 1, 2001-18
Figure 13. Display Interface to Siemens/Intel 8031
Microprocessor (using serial port in mode 0)
Figure 14. Display Interface to Siemens/Intel 8031
Microprocessor (using one bit of parallel port as serial port)
Figure 15. Display Interface with Motorola 68HC05C4
Microprocessor (using SPI port)
Figure 16. Cascading Multiple Displays
VCC
U1
8031
9 RST
18
19
XTAL2
XTAL1
40
RXD
TXD
10
11
22
f
TAN
.01
f
P3.7 17
P3.3 13
P3.4 14
GND
DATA
VCC
CLKSEL
CLK I/O
SDCLK
LD
RST
GND
ID
+
VCC
U1
8031
1
9
20
RST
P1.0
18
19
XTAL2
XTAL1
40 P3.0
P3.1
P3.6
P0.0
10
11
16
39
VCC
22
F
TAN
.01
F
GND
DATA
VCC
CLKSEL
CLK I/O
SDCLK
LD
RST
GND
ID
+
VCC
U1
68HC05C4
1
9
20
RST
PA2
38
39
OSC1
OSC2
40
PA0
PA1
SCLK
MOSI
11
10
33
32
VCC
22
F
TAN
.01
F
GND
DATA
VCC
CS
CLK I/O
SDCLK
LD
RST
GND
ID
+
DATA
SDCLK
LOAD
14 more displays
in between
RST CLK I/O
CLK SEL
RST CLK I/O
CLK SEL
DATA SDCLK
LOAD
Address
Decoder
Chip
0
15
Address Decode 1–14
VCC
RST
DATA
SDCLK
A0
A1
A2
A3
LD
Intelligent Display
CE
Multiple displays can be cascaded using the CLKSEL
and CLK I/O pins (Figure 16). The display designated as
the MasterClock source should have its CLKSEL pin tied
high and the slaves should have their CLKSEL pins tied
low. All CLK I/O pins should be tied together. One dis-
play CLK I/O can drive 15 slave CLK I/Os. Use RST to
synchronize all display counters.
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