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參數資料
| 型號： | SCW1643US-65 |
| 元件分類： | LED |
| 英文描述： | T-1 SINGLE COLOR LED, COOL WHITE, 3.7 mm |
| 封裝： | 5 X 5 MM, 1 MM HEIGHT, ROHS COMPLIANT, CERAMIC,LCC-2 |
| 文件頁數： | 12/15頁 |
| 文件大小： | 419K |
| 代理商： | SCW1643US-65 |
SCE5780
2006-01-23
6
Top View
Dot Matrix Format
Pin Assignment
Pin
Function
Pin
Function
1
CLKSEL
14
Serial Data
2
V
CC (Logic)
15
No connect
3
V
LL (LED)
16
Serial CLK
4
No pin
17
No pin
5
No pin
18
No pin
6
No pin
19
No pin
7
No pin
20
No pin
8
No pin
21
No pin
9
No pin
22
No pin
10
No pin
23
No pin
11
Load
24
Reset
12
GND
25
CLK I/O
13
GND
26
No connect
IDPA5120
01
2
3
45
67
IDOD5217
2.54 (0.100)
0.72
(0.028)
typ.
0.57 (0.022) typ.
4.57
(0.180)
C0 C1 C2 C3 C4
R0
R1
R2
R3
R4
R5
R6
Pin Definitions
Pin
Function
Definitions
1
CLKSEL
H=internal clock, L=external clock
2
V
CC (Logic)
Logic power supply
3
V
LL (LED)
LED power supply
4–10
No pin
No pins in these positions
11
Load
Low input enables data clocking into the 8-bit
serial shift register. When Load goes high, the
contents of the 8-bit serial shift register will be
decoded.
12,13
GND
Power supply ground
14
Serial Data
Serial data input
15
No connect
Pin has no function
16
Serial CLK
For loading data into the 8-bit serial register on
a low to high transition
17–23
No pin
No pins in these positions
24
Reset
Asynchronous input, when low will clear the
Multiplex Counter, User RAM, and Data Regis-
ter. Control Word Register is set to 100%
brightness, maximum peak current, and oscil-
lator divided by 1. The display blanked.
25
CLK I/O
Outputs master clock or input external clock for
display multiplexing.
26
No connect
Pin has no function
Display Column and Row Format
C0
C1
C2
C3
C4
Row 0
1
Row 1
0
1
0
Row 2
0
1
0
Row 3
0
1
0
Row 4
0
1
0
Row 5
0
1
0
Row 6
0
1
0
1=Display dot “On” /// 0=Display dot “Off”
Column Data Ranges
Row 0
00H to 1FH
Row 1
00H to 1FH
Row 2
00H to 1FH
Row 3
00H to 1FH
Row 4
00H to 1FH
Row 5
00H to 1FH
Row 6
00H to 1FH
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