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參數(shù)資料
| 型號： | sda 2526-5 |
| 廠商： | SIEMENS AG |
| 英文描述： | Nonvolatile Memory 1-Kbit EEPROM(非易失性存儲器1K位 EEPROM) |
| 中文描述： | 非易失性內(nèi)存1千位的EEPROM（非易失性存儲器每1000位的EEPROM） |
| 文件頁數(shù)： | 1/12頁 |
| 文件大小： | 267K |
| 代理商： | SDA 2526-5 |
Circuit Description
I
2
C Bus Interface
The
I
2
C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.
It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external
pull-up resistor to
V
CC
(open drain output stage).
The possible operational states of the
I
2
C Bus are shown in
figure 1
. In the quiescent state, both
lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains
"1", information changes on the data bus indicate the start or the end of data transfer between two
components.
The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" is a stop
condition. During a data transfer the information on the data bus will only change while the clock line
SCL is "0". The information on SDA is valid as long as SCL is "1".
In conjunction with an
I
2
C Bus system, the memory component can operate as a receiver and as a
transmitter (slave receiver or slave transmitter). Between a start and stop condition, information is
always transmitted in byte-organized form. Between the falling edge of the eighth clock pulse and
a ninth acknowledge clock pulse, the memory component sets the SDA-line to low as a confirmation
of reception, if the chip select conditions have been met. During the output of data, the data output
of the memory is high in impedance during the ninth clock pulse (acknowledge master).
The signal timing required for the operation of the
I
2
C Bus is summarized in
figure 2
.
Nonvolatile Memory 2-Kbit E
2
PROM
with
I
2
C Bus
Preliminary Data
MOS IC
SDA 2526-5
P-DIP-8-1
Features
G
Word-organized programmable nonvolatile memory in
n-channel floating-gate technology (E
2
PROM)
G
256
×
8-bit organization
G
Supply voltage 5 V
G
Serial 2-line bus for data input and output (
I
2
C Bus)
G
Reprogramming mode, 10 ms erase/write cycle
G
Reprogramming by means of on-chip control (without
external control)
G
Check for end of programming process
G
Data retention > 10 years
G
More than 10
4
reprogramming cycles per address
G
Compatible with SDA 2526. Exceptions: Conditions for
total erase and current consumption
I
CC
Type
Ordering Code
Package
SDA 2526-5
Q67100-H5095
P-DIP-8-1
Semiconductor Group
17
07.94
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SDA2526-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Nonvolatile Memory 2-Kbit E2PROM with I2C Bus |
| SDA253DF | 制造商:SSDI 制造商全稱:Solid States Devices, Inc 功能描述:50A / 400 - 800V THREE PHASE BRIDGE RECTIFIER ASSEMBLY |
| SDA253EF | 制造商:SSDI 制造商全稱:Solid States Devices, Inc 功能描述:50A / 400 - 800V THREE PHASE BRIDGE RECTIFIER ASSEMBLY |
| SDA253F | 制造商:SSDI 制造商全稱:Solid States Devices, Inc 功能描述:50A / 400 - 800V THREE PHASE BRIDGE RECTIFIER ASSEMBLY |
| SDA253FF | 制造商:SSDI 制造商全稱:Solid States Devices, Inc 功能描述:50A / 400 - 800V THREE PHASE BRIDGE RECTIFIER ASSEMBLY |
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