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參數資料
| 型號： | SG7915L |
| 廠商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | NEGATIVE FIXED VOLTAGE REGULATOR |
| 中文描述： | 15 V FIXED NEGATIVE REGULATOR, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 175K |
| 代理商： | SG7915L |
05/01 Rev 1.5
Copyright
1999
∞
1
∞
!"#$ %&
The SG7900A/SG7900 series of negative regulators offer self-contained,
fixed-voltage capability with up to 1.5A of load current. With a variety of
output voltages and four package options this regulator series is an
optimum complement to the SG7800A/SG7800, SG140 line of three
terminal regulators.
These units feature a unique band gap reference which allows the
SG7900A series to be specified with an output voltage tolerance of
±
1.5%.
The SG7900A versions also offer much improved line regulation character-
istics.
All protective features of thermal shutdown, current limiting, and safe-area
control have been designed into these units and since these regulators
require only a single output capacitor (SG7900 series) or a capacitor and
5mA minimum load (SG120 series) for satisfactory performance, ease of
application is assured.
Although designed as fixed-voltage regulators, the output voltage can be
increased through the use of a simple voltage divider. The low quiescent
drain current of the device insures good regulation when this method is
used, especially for the SG120 series.
These devices are available in hermetically sealed TO-257, TO-3, TO-39
and LCC package.
DESCRIPTION
FEATURES
Output voltage set internally to
±
1.5% on SG7900A
Output current to 1.5A
Excellent line and load regulation
Foldback current limiting
Thermal overload protection
Voltages available: -5V, -12V, -15V
Contact factory for other voltage options
Available in surface mount package
HIGH RELIABILITY FEATURES
- SG7900A/SG7900
Available to MIL-STD - 883
MIL-M38510/11501BXA - JAN7905T
MIL-M38510/11505BYA - JAN7905K
MIL-M38510/11502BXA - JAN7912T
MIL-M38510/11506BYA - JAN7912K
MIL-M38510/11503BXA - JAN7915T
MIL-M38510/11507BYA - JAN7915K
LMI level "S" processing available
SCHEMATIC DIAGRAM
**
For normal
operation the (V
OS
)
Sense Pin must be
externally
connected to the
load.
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