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參數(shù)資料
| 型號(hào)： | SH7750 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | SuperH RISC Processor Product Brief |
| 中文描述： | 的SuperH RISC處理器產(chǎn)品簡(jiǎn)介 |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大小： | 58K |
| 代理商： | SH7750 |
SH7750 (SH-4 Series)
SuperH
TM
RISC Processor
Product Brief
TM
SuperH
PROCESSOR
RISC
TM
Description
T
for embedded applications. The SuperH
TM
architecture is
the leader in code density among RISC microprocessors,
reducing memory costs in embedded applications. It
features a 64-bit external data bus, a 16-bit fixed-length
instruction set and a 128-bit vector graphics engine.
T
include handheld PCs, sub-notebook PCs, Internet
appliances, set top boxes, and game machines. The
device can be paired with an ASSP companion device
for a low cost, low IC count, and differentiated system.
H
he SH7750 (SH-4 series) is a high performance, cost-
effective, 2 issue superscalar RISC microprocessor
he SH7750 is used in consumer, computing, multi-
media, and communication markets. Applications
itachi optimized the SH7750 MMU, cache size, and
peripheral mix for Windows
CE applications.
Features
General
- 200 MHz/360 MIPS at 3.3V I/O, 1.8V internal
- 16 x 32-bit general purpose registers
- 256 pin LBGA
CPU
- Code compatible with SH7000/7600/7700 series
- 16 x 32-bit general purpose registers
- 32 x 32-bit single-precision floating point registers
or 16 x 64-bit double-precision floating point registers
or 4 x 128-bit single-precision vector registers and
register matrix
- 16-bit fixed instruction length for high code density
- 32 x 32 + 64 --> 64 bits multiply-accumulate unit for
special functions such as software modems
- MMU Designed for Windows
CE 1KB, 4KB, 64KB,
and 1MB page sizes, 64-entry, fully associative UTLB
- 4 entry, fully associative μITLB
- 5 stage pipeline
Memory
- On-chip cache, 8KB instruction and 16KB data
Write back or write through, selectable by page
Low voltage cache to reduce power consumption
- On-chip bus state controller allows direct
connection to DRAM, SDRAM, SRAM, ROM, and
Flash ROM
8, 16, 32, or 64-bit data bus support
Peripherals
- DMA, 4 channels
- Timers, 3 channels x 32-bits
- Watchdog timer
Two-way superscalar RISC
360 MIPs
Upward compatible with SH-1/2/3
WB/WT,
selectable
by page
Glueless interface to SDRAM,
EDO DRAM, fast page DRAM,
SRAM, and ROM
Integer Unit
32 bit
Instruction
8 KByte
Data
16 KByte
64/32/16/8 bits, 256-pin package
Data
bus
Floating Point Unit
64 bit
Unified TLB
64 entry
Micro ITLB
4 entry
SH-4 CPU
Cache
3D floating point
acceleration hardware
Specialized Math Circuits
DMA controller
Programmable power management
Interrupt controller
Timers
Real-time clock
Serial interface
User break controller
Peripheral Functions
Full Windows CE support
1K/4K/64K/1MByte page sizes
Memory Management Unit
Bus Unit
Hitachi SH-4 RISC Processor
SH-4 Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SH7750 | Hitachi Microcomputer Development Environment System SH7750 E10A Emulator |
| SH7750E10A | Hitachi Microcomputer Development Environment System SH7750 E10A Emulator |
| SH7751 | SuperH RISC engine |
| SH7751R | SuperH RISC engine |
| SH7770 | SH7770 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SH7750E10A | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:Hitachi Microcomputer Development Environment System SH7750 E10A Emulator |
| SH7751 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SuperH RISC engine |
| SH7751R | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SuperH RISC engine |
| SH7760 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SuperHTM RISC engine |
| SH7770 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SH7770 |
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