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參數(shù)資料
| 型號(hào)： | SI5023-D-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 1/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECVRY W/AMP 28MLP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | DSPLL® |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（5x5） |
| 包裝： | 管件 |
| 其它名稱： | 336-1276 |
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Rev. 1.3 6/08
Copyright 2008 by Silicon Laboratories
Si5023
MULTI-RATE SONET/SDH CDR IC WITH LIMITING AMPLIFIER
Features
High-speed clock and data recovery device with integrated limiting amp:
Applications
Description
The Si5023 is a fully-integrated, high-performance limiting amp and clock
and data recovery (CDR) IC for high-speed serial communication systems.
It derives timing information and data from a serial input at OC-48/12/3,
STM-16/4/1, or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data
streams is also provided for OC-48/STM-16 applications that employ
forward error correction (FEC). Use of an external reference clock is
optional. Silicon Laboratories DSPLL technology eliminates sensitive
noise entry points, thus making the PLL less susceptible to board-level
interaction and helping to ensure optimal jitter performance.
The Si5023 represents a new standard in low jitter, low power, small size,
and integration for high-speed LA/CDRs. It operates from a 3.3 V supply
over the industrial temperature range (–40 to 85 °C).
Functional Block Diagram
Supports OC-48/12/3, STM-16/4/
1, Gigabit Ethernet, and 2.7 Gbps
FEC
DSPLL technology
Jitter generation 3.0 mUIrms
(TYP)
Small footprint: 5 x 5 mm
Bit error rate alarm
Reference and referenceless
operation supported
Loss-of-signal level alarm
Data slicing level control
10 mVPP differential sensitivity
3.3 V supply
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
Gigabit Ethernet interfaces
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
Board level serial links
Limiting
Amp
DSPLL
Lock
Detection
Retimer
Reset/
Calibration
Bias Gen.
BUF
CLKOUT+
CLKOUT–
DIN+
DIN–
REFCLK+
REFCLK–
(Optional)
LOS
LOL
REXT
RESET/CAL
SLICE_LVL
DSQLCH
CLK_DSBL
LTR
RATESEL
Signal
Detect
LOS_LVL
BER_LVL
BER
Monitor
DOUT+
DOUT–
2
BERMON
BER_ALM
Ordering Information:
See page 25.
Pin Assignments
Si5023
1
RATESEL0
GND
Pad
Top View
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
22
23
24
25
26
27
28
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
VDD
REXT
RESET/CAL
VDD
DOUT+
DOUT–
GND
BER
M
O
N
BER
_
ALM
BER
_
L
V
L
VD
D
CL
KD
SB
L
CL
KO
U
T
+
CL
KO
U
T
–
LT
R
LOS
DS
QLCH
VD
D
DIN+
DIN–
VD
D
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5023-D-GMR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Limiting amp 3.3 V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5023-EVB | 功能描述:時(shí)鐘和定時(shí)器開(kāi)發(fā)工具 SNT/SDH GbE 2.7Gbps OC48/12/3 STM16/4/1 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5023-X-GM | 制造商:Silicon Laboratories Inc 功能描述: |
| SI-50242-F | 制造商:Bel Fuse 功能描述:- Trays 制造商:BEL STEWART CONNECTOR 功能描述:Bel Stewart, Internal Part #: SI-50242-F 制造商:BEL STEWART CONNECTOR 功能描述:STEWART, INTERNAL PART #: SI-50242-F |
| SI502-EVB | 制造商:SILABS 制造商全稱:SILABS 功能描述:USB plug-in board that allows for evaluation of the Si50x family of CMEMS oscillators. |
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