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參數(shù)資料
| 型號： | SI5364-H-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 1/38頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK SONET/SDH PORT 99LFBGA |
| 標準包裝： | 168 |
| 系列： | DSPLL® |
| 類型： | 時鐘發(fā)生器，扇出緩沖器（分配） |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 675MHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -20°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 99-LBGA |
| 供應商設備封裝： | 99-BGA（11x11） |
| 包裝： | 托盤 |
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Rev. 2.5 8/08
Copyright 2008 by Silicon Laboratories
Si5064
Si5364
SONET/SDH PRECISION PORT CARD CLOCK IC
Features
Applications
Description
The Si5364 is a complete solution for ultra-low jitter high-speed clock generation and
distribution in precision clocking applications, such as OC-192/OC-48 SONET/SDH line/
port cards. This device phase locks to one of three reference inputs in the range of
19.44 MHz and generates four synchronous clock outputs that can be independently
configured for operation in the 19, 155, or 622 MHz range (1, 8, and 32x input clock).
Silicon Laboratories DSPLL technology delivers phase-locked loop (PLL) functionality
with unparalleled performance while eliminating external loop filter components,
providing programmable loop parameters, and simplifying design. The on-chip reference
monitoring and clock switching functions support Stratum 3/3E and SMC compatible
clock switching with excellent output phase transient characteristics. FEC rates are
supported with selectable 255/238 or 238/255 scaling of the clock multiplication ratios.
The Si5364 establishes a new standard in performance and integration for ultra-low jitter
clock generation. It operates from a single 3.3 V supply.
Functional Block Diagram
Ultra-low jitter clock outputs with jitter
generation as low as 0.3 psRMS
No external components (other than a
resistor and standard bypassing)
Up to three clock inputs
Four independent clock outputs at 19,
155, or 622 MHz
Stratum 3, 3E, and SMC compatible
Digital hold for loss-of-input clock
Automatic or manually-controlled hitless
switching between clock inputs
Revertive/non-revertive switching
Loss-of-signal and frequency offset
alarms for each clock input
Support for forward and reverse FEC
clock scaling
8 kHz frame sync output
Low power
Small size (11x11 mm)
SONET/SDH line/port cards
Terabit routers
Core switches
Digital cross connects
FRQSEL_1[1:0]
CLKOUT_1+
CLKOUT_1–
2
DSBLFSYNC
FSYNC
MANCNTRL[1:0]
VALTIME
A_ACTV
LOS_A
FOS_A
LOS_B
FOS_B
LOS_F
REF/CLKIN_F+
REF/CLKIN_F–
CLKIN_B+
CLKIN_B–
CLKIN_A+
CLKIN_A–
AUTOSEL
CAL_ACTV
Signal
Detection,
Selection,
& Control
2
SMC/S3N
DSBLFOS
RVRT
B_ACTV
F_ACTV
DH_ACTV
RSTN/CAL
FEC[1:0]
BWSEL[1:0]
2
CLKOUT_2+
CLKOUT_2–
CLKOUT_3+
CLKOUT_3–
CLKOUT_4+
CLKOUT_4–
FRQSEL_2[1:0]
FRQSEL_3[1:0]
FRQSEL_4[1:0]
SYNCIN
Biasing & Supply
REXT
VSEL33
VDD
GND
÷
2
SiLECTTM
Switching
DSPLLTM
FXDDELAY
INCDELAY
DECDELAY
Ordering Information:
See page 34.
Si5364
Bottom View
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| Si5364-H-GLR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision 19MHz 155MHz 622MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5365 | 制造商:SILABS 制造商全稱:SILABS 功能描述:PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER |
| Si5365/66-EVB | 功能描述:時鐘和定時器開發(fā)工具 Si5365/Si5366 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| Si5365-B-GQ | 功能描述:時鐘合成器/抖動清除器 PIN-PROGRAMMABLE CLK MULTIPLIER 5 OUTS RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5365-B-GQR | 制造商:Silicon Laboratories Inc 功能描述: |
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