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參數資料
| 型號： | SI5365-C-GQR |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數： | 1/28頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK MULTIPLIER PROG 100TQFP |
| 標準包裝： | 250 |
| 系列： | DSPLL® |
| 類型： | 時鐘乘法器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 4:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.05GHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 1.71 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
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Rev. 0.5 2/12
Copyright 2012 by Silicon Laboratories
Si5365
P IN-P ROGRAMMABLE P RECISION C LOCK M ULTIPLIER
Features
Applications
Description
The Si5365 is a low-jitter, precision clock multiplier for high-speed
communication systems, including SONET OC-48/OC-192, Ethernet, and
Fibre Channel, in which the application requires clock multiplication
without jitter attenuation. The Si5365 accepts four clock inputs ranging
from 19.44 to 707 MHz and generates five frequency-multiplied clock
outputs ranging from 19.44 to 1050 MHz. The input clock frequency and
clock multiplication ratio are selectable from a table of popular SONET,
Ethernet, and Fibre Channel frequencies. The Si5365 is based on Silicon
Laboratories' 3rd-generation DSPLL technology, which provides any-
frequency synthesis in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. The DSPLL loop
bandwidth
is
digitally
programmable,
providing
jitter
performance
optimization at the application level. Operating from a single 1.8, 2.5, or
3.3 V supply, the Si5365 is ideal for providing clock multiplication in high
performance timing applications.
Not recommended for new
designs. For alternatives, see the
Si533x family of products.
Selectable output frequencies
ranging from 19.44 to 1050 MHz
Low jitter clock outputs w/jitter
generation as low as 0.6 ps rms
(50kHz–80MHz)
Integrated loop filter with
selectable loop bandwidth
(150 kHz to 1.3 MHz)
Four clock inputs w/manual or
automatically controlled
switching
Five clock outputs with selectable
signal format (LVPECL, LVDS,
CML, CMOS)
Support for ITU G.709 FEC ratios
(255/238, 255/237, 255/236)
LOS alarm outputs
Pin-programmable settings
On-chip voltage regulator for
1.8 ±5%, 2.5 V ±10%, or
3.3 V ±10% operation
Small size: 14 x 14 mm 100-pin
TQFP
Pb-free, RoHS compliant
SONET/SDH OC-48/STM-16
and STM-64/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line
cards
ITU G.709 line cards
Test and measurement
Ordering Information:
See page 21.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SI5365-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5366 | 制造商:SILABS 制造商全稱:SILABS 功能描述:PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR |
| Si5366-B-GQ | 功能描述:鎖相環 - PLL PIN-PROGRAM CLK MULT /JITTER ATTEN 5 OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SI5366-B-GQR | 制造商:Silicon Laboratories Inc 功能描述: |
| Si5366-C-GQ | 功能描述:鎖相環 - PLL PIN-PROGRAM CLK MULT /JITTER ATTEN 5 OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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