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參數資料
| 型號： | SI5600 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SiPHY-TM OC-192/STM-64 SONET/SDH TRANSCEIVER |
| 中文描述： | SiPHY -商標OC-192/STM-64的SONET / SDH收發器 |
| 文件頁數： | 1/28頁 |
| 文件大小： | 365K |
| 代理商： | SI5600 |
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Preliminary Rev. 0.31 8/01
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Copyright 2001 by Silicon Laboratories
Si5600-DS031
Si5600
SiPHY
OC-192/STM-64 SONET/SDH T
RANSCEIVER
Features
Complete low power, high speed, SONET/SDH transceiver with
integrated limiting amp, CDR, CMU, and MUX/DEMUX
!
Data Rates Supported: OC-192/
STM-64, 10GbE, and 10.7 Gbps FEC
!
Low Power Operation 1.2 W (typ)
!
DSPLL Based Clock Multiplier Unit
w/ Selectable Loop Filter Bandwidths
!
Integrated Limiting Amplifier
!
Loss-of-Signal (LOS) Alarm
!
Diagnostic and Line Loopbacks
Applications
Description
The Si5600 is a complete low-power transceiver for high-speed serial
communication systems operating between 9.9 Gbps and 10.7 Gbps. The receive
path consists of a fully integrated limiting amplifier, clock and data recovery unit
(CDR), and 1:16 deserializer. The transmit path combines a low jitter clock
multiplier unit (CMU) with a 16:1 serializer. The CMU uses Silicon Laboratories’
DSPLL
technology to provide superior jitter performance while reducing design
complexity by eliminating external loop filter components. To simplify BER
optimization in long haul applications, programmable slicing, and sample phase
adjustment are supported.
The Si5600 operates from a single 1.8 V supply over the industrial temperature
range (–40
°
C to 85
°
C).
Functional Block Diagram
!
SONET Compliant Loop Timed
Operation
!
Programmable Slicing Level and
Sample Phase Adjustment
!
SFI-4 Compliant Low Speed
Interface
!
Single Supply 1.8 V Operation
!
15 x 15 mm BGA Package
!
Sonet/SDH Transmission
Systems
!
Optical Transceiver Modules
!
Sonet/SDH Test Equipment
DSPLL
TM
TX CM U
TXDOUT
RXDOUT[15:0]
TXDIN[15:0]
RXCLK1
RXCLK2
TXCLK16OUT
FIFORST
RXCLK2DIV
RXCLK2DSBL
FIFOERR
1
D
1
F
TXCLK16IN
RXSQLCH
DLBK
LLBK
TXM SBSEL
RXM SBSEL
TXCLKOUT
TXSQLCH
2
32
2
2
2
2
LPTM
RXDIN
REFCLK
TXLOL
BW SEL
Limiting
AMP
LOSLVL
LOS
LTR
CDR
TXCLKDSBL
2
2
L
TXCLK16IN
REFSEL
2
SLICELVL
PHASEADJ
RXLOL
32
REFRATE
RESET
Control
RESET
÷
÷
Ordering Information:
See page 25.
Si5600
Bottom View
P
RELIMINARY
D
ATA
S
HEET
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