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參數資料
| 型號： | SIPC42S2N08 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | OptiMOS Chip data sheet |
| 中文描述： | 的OptiMOS芯片數據表 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 90K |
| 代理商： | SIPC42S2N08 |
Infineon AG, AI AP APE
, Informations #184R
2002-02-01
1
SIPC42S2N08
Preliminary data
OptiMOS
Chip data sheet
Feature
N-Channel
Enhancement mode
175°C operating temperature
Avalanche rated
d
v
/d
t
rated
Integrated gate resistance
for easy parallel connection
V
DS
R
DS(on)
Die size
Thickness
75
4.2
7 x 6
175
V
m
mm
2
μm
Ordering Code
unsawn wafer on foil
sawn wafer on foil
surf tape
on request
Q67061-S7146
on request
DESCRIPTION
Assembly by epoxy die bonding or soldering
AQL 1.5 for visual inspection according to failure catalog A67207-A7001-A001 issue C
on 100% measured wafer
Storage of chips and wafer according technical guideline 14 Doc. No. A66003-R14-T1-B-35
Maximum Ratings
, at
T
j
= 25 °C, unless otherwise specified
Parameter
Continuous drain current
1)2)
Symbol
I
D
Value
227
Unit
A
T
C
=25°C
Avalanche energy, single pulse
1)
I
D
=80A,
V
DD
=25V,
R
GS
=25
Repetitive avalanche energy, limited by
T
jmax 1)2)
E
AR
Gate source voltage
Additional gate resistance
Operating and storage temperature
E
AS
1070
mJ
50
±20
mJ
V
V
GS
R
G
T
j ,
T
stg
5
±
20%
-55... +175
°C
1Defined by design. Not subject to production test.
2Calculated with
R
thJC
= 0.3 K/W
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