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參數(shù)資料
| 型號(hào)： | SIS600 |
| 廠商： | SILICON INTEGRATED SYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA487 |
| 封裝： | BGA-487 |
| 文件頁數(shù)： | 1/144頁 |
| 文件大小： | 1592K |
| 代理商： | SIS600 |
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SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
i
Silicon Integrated Systems Corporation
CONTENTS
1.
SiS600/SiS5595 OVERVIEW............................................................................................................... 1
2.
FEATURES .............................................................................................................................................. 2
2.1.
SiS600 PCI A.G.P. CONTROLLER..............................................................................................2
2.2.
FUNCTIONAL BLOCK DIAGRAM..................................................................................................5
3.
PIN ASSIGNMENT................................................................................................................................ 6
3.1.
SiS600 PIN ASSIGNMENT (TOP VIEW).......................................................................................6
3.1.1.
SiS600 Pin Assignment (Top View-Left Side)............................................................. 6
3.1.2.
SiS600 Pin Assignment (Top View-Right Side) .......................................................... 7
3.2.
ALPHABETICAL PIN LIST .............................................................................................................8
4.
PIN ASSIGNMENT..............................................................................................................................14
4.1.
SiS600 PIN DESCRIPTION..........................................................................................................14
4.1.1.
Host Bus Interface .........................................................................................................14
4.1.2.
DRAM Controller ..........................................................................................................16
4.1.3.
PCI Interface ..................................................................................................................17
4.1.4.
PCI IDE Interface..........................................................................................................19
4.1.5.
AGP Interface.................................................................................................................20
4.1.6.
Power Pins......................................................................................................................22
4.1.7.
Misc. Pins........................................................................................................................22
5.
FUNCTIONAL DESCRIPTION......................................................................................................24
5.1.
HOST INTERFACE ........................................................................................................................24
5.1.1.
Host INTERFACE BLOCK DIAGRAM .....................................................................24
5.2.
DRAM CONTROLLER ................................................................................................................25
5.2.1.
DRAM Configuration ...................................................................................................25
5.2.1.2.
EDO/FPM DRAM Configuration (4 SIMM/6 SIMM): .....................................25
5.2.1.3.
SDRAM Configuration (2 DIMM/3 DIMM): ....................................................26
5.2.1.4.
DRAM Type Mixed Configuration: EDO/FPM + SDRAM (4 S + 2 DIMM)...26
5.2.2.
DRAM Scramble Table.................................................................................................27
5.2.2.1.
MA mapping table for FPM/EDO DRAM .........................................................27
5.2.2.2.
MA mapping table for SDRAM .........................................................................28
5.2.3.
DRAM Auto-Detection .................................................................................................32
5.2.4.
Arbiter .............................................................................................................................33
5.2.5.
Refresh cycle...................................................................................................................33
5.2.6.
Graphic Window Re-mapping.....................................................................................33
5.3.
PCI BRIDGE..............................................................................................................................35
5.3.1.
PCI Arbiter .....................................................................................................................35
5.3.2.
PCI Bus Interface ..........................................................................................................37
5.3.3.
Target initiated termination ........................................................................................37
5.3.4.
PCI MasteR Controller (PMR) ...................................................................................37
5.3.5.
PCI BURST and POST mode.......................................................................................39
5.3.6.
66Mhz PCI Master Bridge (PMR66) ........................................................................41
5.3.7.
66Mhz PCI Target Bridge (PSL66)............................................................................41
5.4.
A.G.P. COMPLIANT TARGET/HOST-TO-PCI66 BRIDGE ........................................................42
5.5.
POWER MANAGEMENT SUPPORT..............................................................................................43
5.6.
INTEGRATED PCI MASTER/SLAVE IDE CONTROLLER .........................................................43
5.7.
BALL CONNECTIVITY TESTING.................................................................................................48
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