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參數(shù)資料
| 型號： | HM63921 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 560KBITS BRAM 400000 SYSTEM GATES 404 - - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 2048字× 9位CMOS并行的輸出FIFO存儲器 |
| 文件頁數(shù)： | 1/2頁 |
| 文件大小： | 95K |
| 代理商： | HM63921 |
The HM63921 is a first-in, first-out memory that
utilizes a high performance static RAM array with
internal algorithm that controls, monitors and
declares status of the memory by empty flag, full
flag and half-full flag, to prevent data overflow or
underflow.
Expansion logic warrants unlimited expansion
capability in width and depth. Both read and write
are independent from each other and their
corresponding pointers are designed to select the
proper locations out of the entire array serially
without address information to load or unload data.
Data is toggled in and out of the device through the
use of the write enable (
W
) and read enable (
R
)
pins. The device has a read/write cycle time of
30/35/45 ns. Organization of HM63921 provides a
9-bit data bus. The ninth bit could be used for
control or parity for error checking at the option of
the user. The HM63921 is fabricated using the
Hitachi CMOS 1.3 micron technology. The device
is available in DIP and SOJ.
Features
First-in, first-out dual port memory
2 k
×
9 organization
Low-power CMOS 1.3 micron technology
Asynchronous and simultaneous read and write
Fully expandable in depth and/or width
Single 5 V power supply
Empty and full warning flags
Half-full flag
Access time: 22/25/35 ns
Package: 300-mil 28-pin plastic DIP package
300-mil 28-pin plastic SOJ package
Pin Arrangement
Ordering Information
Type name
–––––––––––––––––––––––––––––––––––––––––
HM63921P-20R
22 ns
––––––––––––––––––––––––––––
plastic DIP
HM63921P-25
25 ns
––––––––––––––––––––––––––––
HM63921P-35
35 ns
–––––––––––––––––––––––––––––––––––––––––
HM63921JP-20R 22 ns
––––––––––––––––––––––––––––
plastic SOJ
HM63921JP-25
25 ns
––––––––––––––––––––––––––––
HM63921JP-35
35 ns
–––––––––––––––––––––––––––––––––––––––––
Access time
Package
300-mil 28-pin
(DP-28NA)
300-mil 28-pin
(CP-28DN)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
W
D8
D3
D2
D1
D0
XI
FF
Q0
Q1
Q2
V
CC
D4
D5
D6
D7
FL/RT
RS
EF
XO/HF
Q7
Q6
Q5
Q4
R
28
27
26
25
24
23
22
21
20
19
18
17
Q3
Q8
V
SS
16
15
(Top view)
1
HM63921 Series
2048-word
×
9-bit CMOS Parallel In-Out FIFO Memory
相關PDF資料 |
PDF描述 |
|---|---|
| HM63921P-20R | 560KBITS BRAM 400000 SYSTEM GATES 404 I/ - NOT RECOMMENDED for NEW DESIGN |
| HM63921P-25 | 560KBITS BRAM 400000 SYSTEM GATES 404 - - NOT RECOMMENDED for NEW DESIGN |
| HM63921P-35 | 2048-word x 9-bit CMOS Parallel In-Out FIFO Memory |
| HM65256B | 32.768-WORD X 8-BIT HIGH SPEED PSUEDO STATIC RAM |
| HM65256BLSP-10T | 32.768-WORD X 8-BIT HIGH SPEED PSUEDO STATIC RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HM63921JP-20R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2048-word x 9-bit CMOS Parallel In-Out FIFO Memory |
| HM63921JP-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2048-word x 9-bit CMOS Parallel In-Out FIFO Memory |
| HM63921JP-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2048-word x 9-bit CMOS Parallel In-Out FIFO Memory |
| HM63921P-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x9 Asynchronous FIFO |
| HM63921P-20R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2048-word x 9-bit CMOS Parallel In-Out FIFO Memory |
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