- 您現在的位置：買賣IC網 > PDF目錄180224 > M5LV-128/68-5VC (LATTICE SEMICONDUCTOR CORP) Fifth Generation MACH Architecture PDF資料下載
參數資料
| 型號： | M5LV-128/68-5VC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | EE PLD, 5.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 1/42頁 |
| 文件大小： | 938K |
| 代理商： | M5LV-128/68-5VC |
當前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
Publication# 20446
Rev: J
Amendment/0
Issue Date: April 2002
MACH 5 CPLD Family
Fifth Generation MACH Architecture
FEATURES
◆
High logic densities and I/Os for increased logic integration
— 128 to 512 macrocell densities
— 68 to 256 I/Os
◆
Wide selection of density and I/O combinations to support most application needs
—6 macrocell density options
—7 I/O options
—Up to 4 I/O options per macrocell density
—Up to 5 density & I/O options for each package
◆
Performance features to t system needs
— 5.5 ns tPD Commercial, 7.5 ns tPD Industrial
— 182 MHz fCNT
— Four programmable power/speed settings per block
◆
Flexible architecture facilitates logic design
—Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
—Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
◆
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— IEEE 1149.1 compliant for boundary scan testing
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Bus-Friendly Inputs & I/Os
— Individual output slew rate control
—Hot socketing
— Programmable security bit
◆
Advanced E2CMOS process provides high performance, cost effective solutions
相關PDF資料 |
PDF描述 |
|---|---|
| M5LV-128/68-7VC | Fifth Generation MACH Architecture |
| M5LV-128/68-7VI | Fifth Generation MACH Architecture |
| M5LV-384/160-20YI | Fifth Generation MACH Architecture |
| M5LV-384/160-6YC | Fifth Generation MACH Architecture |
| M5LV-384/160-7YC | Fifth Generation MACH Architecture |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M5LV-256/104-10AC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10AI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10VC | 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
發布緊急采購，3分鐘左右您將得到回復。