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參數資料
| 型號： | PA7540JN-15 |
| 英文描述： | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
| 中文描述： | PA7540果皮陣列？電可擦除可編程邏輯陣列 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 239K |
| 代理商： | PA7540JN-15 |
1
04-02-051B
PA7540 PEEL Array
Programmable Electrically Erasable Logic Array
Most Powerful 24-pin PLD Available
- 20 I/Os, 2 inputs/clocks, 40 registers/latches
- 40 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried
Ideal for Combinatorial, Synchronous and
Asynchronous Logic Applications
- Integration of multiple PLDs and random logic
- Buried counters, complex state-machines
- Comparators, decoders, multiplexers and other wide-
gate functions
High-Speed Commercial and Industrial Versions
- As fast as 10ns/15ns (tpdi/tpdx), 71.4MHz (f
MAX
)
- Industrial grade available for 4.5 to 5.5V V
CC
and
-40 to +85 °C temperatures
CMOS Electrically Erasable Technology
- Reprogrammable in 24-pin DIP, SOIC and
28-pin PLCC packages
- Optional JN package for 22V10 power/ground
compatibility
Flexible Logic Cell
- 2 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets,
clock polarity and output enables
- Sum-of-products logic for output enables
Development and Programmer Support
- Anachip’s WinPLACE Development Software
- Fitters for ABEL, CUPL and other software
- Programming support by popular third-party
programmers
General Description
The PA7540 is a member of the Programmable Electrically
Erasable Logic (PEEL) Array family based on ICT’s
CMOS EEPROM technology. PEEL Arrays free
designers from the limitations of ordinary PLDs by
providing the architectural flexibility and speed needed for
today’s programmable logic designs. The PA7540 is by far
the most powerful 24-pin PLD available today with 20 I/O
pins, 2 input/global-clocks and 40 registers/latches (20
buried logic cells and 20 I/O registers/latches). Its logic
array implements 84 sum-of-products logic functions. The
PA7540’s logic and I/O cells (LCCs, IOCs) are extremely
flexible offering two output functions per cell (a total of 40
for all 20 logic cells). Logic cells are configurable as D, T,
and JK registers with independent or global clocks, resets,
Figure 1. Pin Configuration
presets, clock polarity, and other features, making the
PA7540
suitable
for
a
synchronous and asynchronous logic applications. With pin
compatibility and super-set functionality to most 24-pin
PLDs, (22V10, EP610/630, GAL6002), the PA7540 can
implement designs that exceed the architectures of such
devices. The PA7540 supports speeds as fast as
10ns/15ns (tpdi/tpdx) and 71.46MHz (f
MAX
) at moderate
power consumption 80mA (55mA typical). Packaging
includes 24-pin DIP, SOIC and 28-pin PLCC (see Figure
1). Anachip and popular third-party development tool
manufacturers provide development and programming
support for the PA7540.
variety
of
combinatorial,
DIP
I/CLK1
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
GND
12
VCC
24
I/O
23
I/O
22
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/CLK2
13
1
2
3
4
5
6
7
8
9
10
11
12
I/CLK1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/CLK2
SOIC
PLCC-JN
08-14-001B
12
I
13
I
14
G
15
N
16
I
17
I
18
I
25
I/O
24
I/O
23
I/O
22
NC
21
I/O
20
I/O
19
I/O
4
I
3
I
2
I
1
N
28
V
27
I
26
I
5
I/O
6
I/O
7
I/O
8
NC
9
I/O
10
I/O
11
I/O
5
I/O
6
I/O
7
I/O
8
NC
9
I/O
10
I/O
11
I/O
12
I
13
I
14
G
15
G
16
I
17
I
18
I
4
I
3
I
2
I
1
V
28
V
27
I
26
I
PLCC-J
25
I/O
24
I/O
23
I/O
22
NC
21
I/O
20
I/O
19
I/O
Figure 2. Block Diagram
PA7540
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/CLK2
GND
I/CLK1
I/O
I/O
I/O
I/O
I/O
I/O
Global Cells
I/O Cells
I/O
I/O
I/O
I/O
I/O
I/O
Logic Control Cells
2 Input/
Global Clock Pins
Global
Cells
2
I/O
Cells
(IOC)
Logic
Control
Cells
(LCC)
20
20
20
20
A
B
C
D
84 (42X2)
Array Inputs
true and
complement
Buried
logic
4 sum terms
4 product terms
for Global Cells
20 Logic Control Cells
2 output functions per cell
(40 total output functions possible)
Logic functions
to I/O cells
20 I/O Pins
80 sum terms
(four per LCC)
Logic
Array
08-14-002A
相關PDF資料 |
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| PA7540JNI-15 | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
| PA7540J-15 | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
| PA7540 | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
| PA7540P-15 | PA7540 PEEL Array? Programmable Electrically Erasable Logic Array |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| PA7540JN-15L | 功能描述:EEPLD - 電子擦除可編程邏輯設備 2 Input 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數:8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-20 |
| PA7540JNI-15 | 功能描述:EEPLD - 電子擦除可編程邏輯設備 2 INP 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數:8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-20 |
| PA7540JNI-15L | 功能描述:EEPLD - 電子擦除可編程邏輯設備 2 Input 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數:8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-20 |
| PA7540P-15 | 功能描述:EEPLD - 電子擦除可編程邏輯設備 2 INP 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數:8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-20 |
| PA7540P-15L | 功能描述:EEPLD - 電子擦除可編程邏輯設備 2 Input 20 I/O 15ns RoHS:否 制造商:Atmel 邏輯系列:ATF16V8BQL 最大工作頻率:62 MHz 可編程輸入/輸出端數量:20 電源電流:20 mA 延遲時間:15 ns 每個宏指令的積項數:8 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 大電池數量:8 最小工作溫度:- 40 C 最大工作溫度:+ 85 C 安裝風格:Through Hole 封裝 / 箱體:PDIP-20 |
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