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參數資料
| 型號： | VIRTEXQPRO |
| 英文描述： | QPro Virtex 2.5V QML High-Reliability FPGAs |
| 中文描述： | QPro的Virtex 2.5V的QML第高可靠性的FPGA |
| 文件頁數： | 1/4頁 |
| 文件大小： | 37K |
| 代理商： | VIRTEXQPRO |
2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm
.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-1 (v2.5 ) April 2, 2001
Product Specification
1-800-255-7778Module 1 of 4
1
Features
Fast, high-density Field-Programmable Gate Arrays
-
Densities from 50k to 1M system gates
-
System performance up to 200 MHz
-
66-MHz PCI Compliant
-
Hot-swappable for Compact PCI
Multi-standard SelectIO interfaces
-
16 high-performance interface standards
-
Connects directly to ZBTRAM devices
Built-in clock-management circuitry
-
Four dedicated delay-locked loops (DLLs) for
advanced clock control
-
Four primary low-skew global clock distribution
nets, plus 24 secondary local clock nets
Hierarchical memory system
-
LUTs configurable as 16-bit RAM, 32-bit RAM,
16-bit dual-ported RAM, or 16-bit Shift Register
-
Configurable synchronous dual-ported 4k-bit
RAMs
-
Fast interfaces to external high-performance RAMs
Flexible architecture that balances speed and density
-
Dedicated carry logic for high-speed arithmetic
-
Dedicated multiplier support
-
Cascade chain for wide-input functions
-
Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset
-
Internal 3-state bussing
-
IEEE 1149.1 boundary-scan logic
-
Die-temperature sensor diode
Supported by FPGA Foundation and Alliance
Development Systems
-
Complete support for Unified Libraries, Relationally
Placed Macros, and Design Manager
-
Wide selection of PC and workstation platforms
SRAM-based in-system configuration
-
Unlimited re-programmability
-
Four programming modes
0.22
m
m 5-layer metal process
100% factory tested
Description
The Virtex FPGA family delivers high-performance,
high-capacity programmable logic solutions. Dramatic
increases in silicon efficiency result from optimizing the new
architecture for place-and-route efficiency and exploiting an
aggressive 5-layer-metal 0.22
m
m CMOS process. These
advances make Virtex FPGAs powerful and flexible alterna-
tives to mask-programmed gate arrays. The Virtex family
comprises the nine members shown in
Table 1
.
Building on experience gained from previous generations of
FPGAs, the Virtex family represents a revolutionary step
forward in programmable logic design. Combining a wide
variety of programmable system features, a rich hierarchy of
fast, flexible interconnect resources, and advanced process
technology, the Virtex family delivers a high-speed and
high-capacity programmable logic solution that enhances
design flexibility while reducing time-to-market.
0
Virtex 2.5 V
Field Programmable Gate Arrays
DS003-1 (v2.5 ) April 2, 2001
0
3
Product Specification
R
Table 1:
Virtex Field-Programmable Gate Array Family Members
Device
System Gates
CLB Array
Logic Cells
Maximum
Available I/O
Block RAM
Bits
Maximum
SelectRAM+
Bits
XCV50
57,906
16x24
1,728
180
32,768
24,576
XCV100
108,904
20x30
2,700
180
40,960
38,400
XCV150
164,674
24x36
3,888
260
49,152
55,296
XCV200
236,666
28x42
5,292
284
57,344
75,264
XCV300
322,970
32x48
6,912
316
65,536
98,304
XCV400
468,252
40x60
10,800
404
81,920
153,600
XCV600
661,111
48x72
15,552
512
98,304
221,184
XCV800
888,439
56x84
21,168
512
114,688
301,056
XCV1000
1,124,022
64x96
27,648
512
131,072
393,216
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