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參數(shù)資料
| 型號： | SK100E016PJ |
| 廠商： | Semtech Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Bit Synchronous Binary Up Counter |
| 中文描述： | 8位二進(jìn)制計(jì)數(shù)器同步最多 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 153K |
| 代理商： | SK100E016PJ |
The SK10E/100E111 is a low skew 1-to-9 differential
driver designed with clock distribution in mind. It accepts
one signal input which can be either differential or single-
ended if the VBB output is used. The signal is fanned
out to 9 identical differential outputs. An enable input
is also provided. A HIGH disables the device by forcing
all Q outputs LOW and all Q* outputs HIGH.
The device is specifically designed, modeled, and
produced with low skew as the key goal. Optimal design
and layout serve to minimize gate-to-gate skew within-
device, and characterization is used to determine process
control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed
low skew device.
To ensure that the tight skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50
, even if only one side is being used.
In most applications, all nine differential pairs will be
used and therefore terminated. In the case where fewer
than nine pairs are used, it is necessary to terminate at
least the output pairs on the same package side (i.e.
sharing the same V
CCO
) as the pair(s) being used on
that side in order to maintain minimum skew. Failure to
do this will result in small degradations of propagation
delay (on the order of 10–20ps) of the output(s) being
used which, while not being catastrophic to most designs,
will mean a loss of skew margin.
!"#$
%&
Low Skew
Guaranteed Skew Spec
Differential Design
V
BB
Output
Enable Input
Extended 100E V
EE
Range of –4.2 to –5.5V
75K
Internal Input Pulldown Resistors
Fully Compatible with MC10E111 and
MC100E111
Specified Over Industrial Temperature Range:
–40
o
C to 85
o
C
ESD Protection of >4000V
Available in 28-pin PLCC Package
Q0
Q0*
Q1
Q1*
Q2
Q2*
Q3
Q3*
Q4
Q4*
Q5
Q5*
Q6
Q6*
Q7
Q7*
Q8
Q8*
IN
IN*
EN*
VBB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SK100E016PJT | 8-Bit Synchronous Binary Up Counter |
| SK100E111PJ | 1:9 Differential Clock Driver |
| SK100E116PJ | Box-shaped pin header, Discrete wire crimping connection, Discrete wire connectors; HRS No: 543-0622-0 00; No. of Positions: 10; Connector Type: Panel; Contact Gender: Male; Contact Spacing (mm): 2; Terminal Pitch (mm): 2; Current Rating(Amps)(Max.): 2; Operating Temperature Range (degrees C): -30 to 85; General Description: In-line plug; Male contact; Pin contact termination |
| SK100E116PJT | Quint Differential Line Receiver |
| SK100E131PJ | 4-Bit D Flip-Flop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SK100E016PJT | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:8-Bit Synchronous Binary Up Counter |
| SK100E111 | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:1:9 Differential Clock Driver |
| SK100E111PJ | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:1:9 Differential Clock Driver |
| SK100E111PJT | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:1:9 Differential Clock Driver |
| SK100E116 | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Quint Differential Line Receiver |
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