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參數資料
型號: SK10E116PJT
廠商: Semtech Corporation
英文描述: TRANS NPN 100VCEO 5A TOP-3F
中文描述: 昆特差分線路接收器
文件頁數: 1/4頁
文件大小: 112K
代理商: SK10E116PJT
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The SK10/100E116 is a quint differential line receiver
designed for use in new, high-performance ECL systems.
The receiver design features clamp circuitry to cause a
defined output state if both the inverting and non-inverting
inputs are left open; in this case the Q output goes low,
while the Q* output goes high. This feature makes the
device ideal for twisted pair applications.
If both inverting and non-inverting inputs are at an equal
potential of >–2.9V, the receiver does
not
go to a defined
state, but rather shares current in normal differential
amplifier fashion, producing output voltage levels midway
between high and low. This may even cause the device to
oscillate.
The SK10/100E116 provides VBB output for either single-
ended use or as a DC bias for AC coupling to the device.
The VBB output pin should be used only as a DC bias for
the E116 as its current sink/source capability is limited.
Whenever used, the VBB pin should be bypassed to VCC
via a 0.01 μF capacitor.
500 ps Maximum Propagation Delay
Extended VEE Range of –4.2V to –5.5V
VBB Output for Single-Ended Reception
Internal 75K
Input Pull-Down Resistors
ESD Protection of >4000V
Fully Compatible with MC10E/100E116
Specified Over Industrial Temperature Range:
–40
o
C to +85
o
C
Available in 28-Pin PLCC Package
26
27
28
1
2
3
4
18
17
16
15
14
13
12
2
2
2
2
2
2
1
D
D
D
V
Q
Q
V
Q3*
Q3
VCC
Q2*
Q2
VCC0
Q1*
D3*
D2
D2*
VEE
VBB
D0
D0*
D
D
V
Q
Q
V
Q
5
6
7
8
9
1
1
PLCC
TOPVIEW
Q0
Q0*
D0
D0*
Q1
Q1*
D1
D1*
Q2
Q2*
D2
D2*
Q3
Q3*
D3
D3*
Q4
Q4*
D4
D4*
VBB
相關PDF資料
PDF描述
SK100E116 Quint Differential Line Receiver(100K系列,五差分線接收器)
SK10E142 9-Bit Shift Register
SK10E142PJ 9-Bit Shift Register
SK10E142PJT 9-Bit Shift Register
SK100E142 9-Bit Shift Register(100K系列,9位移位寄存器(屬高速ECL邏輯系列))
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