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參數(shù)資料
型號: SK10EL15WU
廠商: Semtech Corporation
英文描述: 1:4 Clock Distribution
中文描述: 1:4時鐘分配
文件頁數(shù): 1/4頁
文件大小: 92K
代理商: SK10EL15WU
Revision 1/February 12, 2001
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The SK10/100EL15W is a low skew 1:4 clock distribution
chips designed explicitly for low skew clock distribution
applications. This device is fully compatible with
MC10EL15 & MC100EL15. The device can be driven by
either a differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. If a single-ended
input is to be used, the VBB output should be connected
to the CLK* input and bypassed to VCC via a 0.01 μF
capacitor. The EL15W provides a VBB output for either
single-ended use or as a DC bias for AC coupling to the
device. The VBB pin should be used only as a bias for
EL15W as its current sink/source capability is limited.
Whenever used, the VBB pin should be bypassed to VCC
via a 0.01 μF capacitor.
The EL15W features a multiplexed clock input to allow for
the distribution of a lower speed scan or test clock along
with the high speed system clock. When LOW (or left
open and pulled LOW by the input pull-down resistor) the
SEL pin will select the differential clock input.
The common enable (EN*) is synchronous so that the
outputs will only be enabled/disabled when they are already
in the LOW state. This avoids any chance of generating a
runt clock pulse when the device is enabled/disabled as
can happen with an asynchronous control. The internal
flip-flop is clocked on the falling edge of the input clock,
therefore, all associated specification limits are referenced
to the negative edge of the clock input.
Extended Supply Voltage Range: (VEE = –5.5V to
–3.0V, VCC = 0V) or (VCC = + 3.0V to +5.5V,
VEE=0V)
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
75K
Internal Input Pull-Down Resistors
Fully Compatible with MC10EL15 and
MC100EL15
Specified Over Industrial Temperature Range:
–40
o
C to +85
o
C
ESD Protection of >4000V
Available in 16-Pin SOIC Package
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!" # !"
Q0
Q0*
Q2
Q2*
Q3
Q3*
Q1
Q1*
VCC
EN*
CLK*
VBB
SEL
VEE
SCLK
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q D
1
0
相關PDF資料
PDF描述
SK100EL15WU 1:4 Clock Distribution
SK10EL15W 1:4 Clock Distribution
SK10EL15WD 1:4 Clock Distribution
SK100EL15W 1:4 Clock Distribution
SK100EL15WD 1:4 Clock Distribution
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