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參數(shù)資料
| 型號： | SL2305SC-1HT |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-8 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 150K |
| 代理商： | SL2305SC-1HT |
Rev 2.1, October 22, 2007
Page 1 of 11
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL2305
Key Features
10 to 140 MHz operating frequency range
Low output clock jitter:
- 140 ps-max c-c-j at 66 MHz
Low output-to-output skew: 150 ps-max
Low product-to-product skew: 400 ps-max
3.3 V power supply range
Low power dissipation:
- 14 mA-max at 66MHz
- 26 mA-max at 133 MHz
One input drives 5 outputs organized as 4+1
SpreadThru PLL that allows use of SSCG
Standard and High-Drive options
Available in 8-pin SOIC and TSSOP packages
Available in Commercial and Industrial grades
Applications
Printers and MFPs
Digital Copiers
PCs and Work Stations
DTV
Routers, Switchers and Servers
Digital Embeded Systems
Description
The SL2305 is a low skew, low jitter and low power Zero
Delay Buffer (ZDB) designed to produce up to five (5) clock
outputs from one (1) reference input clock for high speed
clock distribution applications. The product has an on-chip
PLL which locks to the input clock at CLKIN and receives its
feedback internally from the CLKOUT pin.
The SL2305 is available with two (2) drive strength versions.
The -1 is the standard-drive version and -1H is the high-
drive version.
The SL2305 high-drive version operates up to 140MHz and
the standard drive version -1 operates up to 100.
The SL2305 enter into Power-Down (PD) mode if the input
at CLKIN is DC (0 to VDD). In this power-down state all five
(5) outputs are tri-stated and the PLL is turned off leading to
less than 12
μA-max of power supply current draw.
Benefits
Up to five (5) distribution of input clock
Standard and High-Drive levels to control impedance
level, frequency range and EMI
Low jitter and skew
Low power dissipation
Low cost
Block Diagram
PLL
VDD
GND
CLKIN
CLKOUT
CLK1
CLK2
CLK3
CLK4
Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)
相關PDF資料 |
PDF描述 |
|---|---|
| SL2305SC-1H | 2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL2305ZC-1H | 2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL2305SC-1H | 2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL2305SI-1T | 2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL2305ZC-1T | 2305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SL2305SC-1T | 功能描述:時鐘緩沖器 10-140MHz 5 Outputs ZDB 3.3V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL2305SI-1 | 功能描述:時鐘緩沖器 10-140MHz 5 Outputs ZDB 3.3V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL2305SI-1H | 功能描述:時鐘緩沖器 10-140MHz 5 Outputs ZDB 3.3V High Drive RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL2305SI-1HT | 功能描述:時鐘緩沖器 10-140MHz 5 Outputs ZDB 3.3V High Drive RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL2305SI-1T | 功能描述:時鐘緩沖器 10-140MHz 5 Outputs ZDB 3.3V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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