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參數(shù)資料
| 型號： | SL23EP05IT-1 |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, SOIC-8 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 154K |
| 代理商： | SL23EP05IT-1 |
Rev 0.0, September 18, 2006
Page 1 of 11
2400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
SL23EP05
Key Features
10 to 220 MHz operating frequency range
Low output clock jitter:
20 ps-typ cycle-to-cycle jitter
15 ps-typ period jitter
Low output-to-output skew: 30 ps-typ
Low product-to-product skew: xx ps-typ
Wide 2.5 V to 3.3 V power supply range
Low power dissipation:
12 mA-typ at 66 MHz and VDD=3.3 V
10 mA-typ at 66 MHz and VDD=2.5V
One input drives 5 outputs organized as 4+1
SpreadThru PLL that allows use of SSCG
Standard and High-Drive options
Available in 150 mil 8-pin SOIC package
Available in Commercial and Industrial grades
Applications
Printers and MFPs
Digital Copiers
PCs and Work Stations
Routers, Switchers and Servers
Digital Embeded Systems
Description
The SL23EP05 is a low skew, low jitter and low power Zero Delay
Buffer (ZDB) designed to produce up to five (5) clock outputs from
one (1) reference input clock for high speed clock distribution
applications. The product has an on-chip PLL which locks to the
input clock at CLKIN and receives its feedback internally from the
CLKOUT pin.
The SL23EP05 is available with two (2) drive strength versions
called -1 and -1H. The -1 is the standard-drive version and -1H is
the high-drive version.
The SL23EP05 high-drive version operates up to 220MHz and
200MHz at 3.3V and 2.5V power supplies respectively. The
standard drive version -1 operates up to 167MHz and 133MHz at
3.3V and 2.5V respectively.
The SL23EP05 enter into Power Down (PD) mode if the input at
CLKIN is less then 2.0MHz or there is no rising edge. In this state
all five (5) outputs are tri-stated and the PLL is turned off leading
to less than 25
μA of power supply current draw.
Benefits
Up to five (5) distribution of input clock
Standard and High-Dirive levels to control impedance
level, frequency range and EMI
Low power dissipation, jitter and skew
Low cost
Block Diagram
PLL
VDD
GND
CLKIN
CLKOUT
CLK1
CLK2
CLK3
CLK4
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SL23EP05SI-1 | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL23EP05SI-1HT | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL23EP05SI-1 | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL23EP05SI-1T | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| SL23EP08SC-2HT | 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL23EP05SC-1 | 功能描述:時鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP05SC-1H | 功能描述:時鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V Hi Drv RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP05SC-1HT | 功能描述:時鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V Hi Drv RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP05SC-1T | 功能描述:時鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| SL23EP05SI-1 | 功能描述:時鐘緩沖器 10-220MHz 5 Outputs ZDB 3.3-2.5V RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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