
1
Master
2-layer Metal
3-layer Metal
SLA4028
SLA402T
28,260
14,130
24,868
116
(128)
SLA4046
SLA404T
46,864
22,026
39,834
144
(164)
SLA4078
SLA407T
78,600
35,370
62,880
184
(212)
SLA4115
SLA411T
115,388
51,924
86,541
216
(256)
tpd = 0.160ns (standard at 3.3V)
SLA4162
SLA416T
162,864
70,031
122,148
256
(304)
SLA4239
SLA423T
239,468
95,787
167,627
308
(368)
SLA4318
SLA431T
318,308
127,323
222,815
352
(424)
SLA4411
SLA441T
411,257
164,502
287,879
400
(480)
Features
Total BCs (Raw Gates)
Usable BCs
2-layer Metal
3-layer Metal
Number of PADs
(In Case of Micro Pitch)
Propagation
Delay
Internal Gates
Input Gates
Output Buffers
tpd = 0.400ns (standard at 5.0V) level shifter, tpd = 0.420ns (standard at 3.3V)
tpd = 1.99ns (standard at 5.0V) level shifter, tpd = 1.89ns (standard at 3.3V) CL = 50pF
CMOS, TTL, PCI, USB*, LVDS*
LVTTL, TTL, CMOS, Pull-up/Pull-down, Schmitt, 2.0/3.0/3.3/5.0V Level interface (Level shifter)
Normal, Open drain, 3-state, Bi-directional, 2.0/3.0/3.3/5.0V Level interface (Level shifter)
I/O Level
Input Mode
Output Mode
* Under development
PF842-02
SLA40000 Series
High Density Gate Array
I
OVERVIEW
The SLA 40000 series are super-high-density/speed, Sea-of-gate type CMOS gate arrays adopting the 0.45é m
process.
They consume less electricity, a feature of ASICs dedicated to 3.3V, while enabling high-speed-operation as well
as 3V/5V full swing I/F in the level shifter.
There are 2- and 3-metal layer for each of 8 models from 28,260 to 411,257 gates, satisfying customer needs for
a wide range of circuit size.
In addition, the series can be used with various I/F devices such as low noise output cells, PCI I/F revision 2.0, GTL
I/F*, JTAG*, fail/safe output* and test control input*, and have diverse applications such as small information
instrument and for image processing.
To develop high-speed/high-density circuits in a shorter period of time, the series enable diverse design techniques
to be used during development such as high accuracy simulation of interconnection resistance and blunted
waveform in addition to the conventional interconnection capacity components, and provide a new layout tool for
reducing clock skew.
I
FEATURES
G
Super-high density (adopting 0.45
μ
m silicon gate CMOS with 2- and 3-metal layers)
G
High-speed operation (operation delay of internal gate = 0.160ns at 3.3V, 2-input power NAND standard)
G
Internal gate = 3.3 and 3.0V (2.0V single), I/O buffer = 5.0, 3.3 and 3.0V (2.0V single) (built-in level shifter)
G
Low power consumption (0.80
μ
W/MHz/BC when internal cell = 3.0V)
G
Output drivability (I
OL
= 100
μ
, 1, 3, 6, 12, 24 mA when PCI = 5.0V, I
OL
= 100
μ
, 1, 2, 6, 12mA when PCI = 3.3V,
I
OL
= 50
μ
, 300
μ
, 600
μ
, 2, 4mA when 2.0V)
G
RAM, PLL, IrDA*, and various function cells available
G
Low noise output cell, PCI I/F, USB I/F*, LVDS*, JTAG
I
PRODUCT LINEUP
G
Super-high-density/speed gate array
G
Operates on 3.3 and 3.0V power source
(level shifter is pre-installed)
G
Raw of gates: 28 to 411k gates
(sea of gates)