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參數資料
| 型號： | SLA944F |
| 廠商： | 愛普生（中國）有限公司 |
| 英文描述： | High speed, high integration gate array |
| 中文描述： | 高速，高集成度門陣列 |
| 文件頁數： | 1/2頁 |
| 文件大小： | 26K |
| 代理商： | SLA944F |
1
PF841-03
SLA9000F Series
G
High speed, high integration gate array.
G
Number of gates mounted: 2.7K to 44K gates.
I
DESCRIPTION
The SLA9000F series is a SOG type CMOS gate which has realized high speed, high integration and high
driving capability. This series is offered with 2,784 to 44,070 gates to ensure an optimum application for any
mid size high speed systems.
This series is designed to operate on both 5 V and 3 V systems to correspond to increasing low-voltage
oriented applications. Simplified level shifter cell is available on this series. And, the
μ
A order low noise output
cell of the series has made it suitable for small size, handy equipments and many other applications.
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FEATURES
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Super-high density (adopting 1.0
μ
m silicon gate CMOS with 2-metal layer)
G
High-speed operation (operation delay of internal gate = 0.3ns at 5.0V, 2-input Power NAND standard)
G
Simplified level shifter cells available
G
Output drivability (I
OL
= 0.1, 2, 6, 12, 24 mA when 5.0V, I
OL
= 0.1, 1, 3, 6, 12mA when 3.3V)
G
On-chip RAM available
G
Low noise output cells available
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PRODUCT LINEUP
Master
SLA902F
SLA904F
SLA907F
SLA909F
SLA913F
SLA919F
SLA927F
SLA944F
Total BCs (Raw Gates)
Usable Bcs
Number of PADs
2,784
1,809
80
4,392
2,854
100
7,872
4,723
128
9,540
5,724
144
13,144
7,229
160
19,350
10,642
184
27,234
13,617
208
44,070
22,035
256
Propagation
Delay
Internal Gates
Input Buffers
Output Buffers
tpd = 0.30ns (standard at 5.0V), tpd = 0.43ns (standard at 3.3V)
tpd = 0.91ns (standard at 5.0V), tpd = 1.08ns (standard at 3.3V)
tpd = 3.5ns (standard at 5.0V), tpd = 4.2ns (standard at 3.3V) CL = 50pF
TTL, CMOS
TTL, CMOS, Pull-up/Pull-down, Schmitt, 3.0/3.3/5.0V Level interface
Normal, Open drain, 3-state, Bi-directional, 3.0/3.3/5.0V Level interface
I/O Level
Input Mode
Output Mode
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