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參數(shù)資料
| 型號： | SLGSSTU32864EX-TR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DDR2 Configurable Registered Buffer |
| 中文描述： | 注冊緩沖DDR2內(nèi)存配置 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 206K |
| 代理商： | SLGSSTU32864EX-TR |
Silego Technology Inc.
(408) 327-8800
SLGSSTU32864E
1
PRELIMINARY
Data is subject to change.
Mar 5, 2004
DDR2 Configurable Registered Buffer
Features:
Compatible with JEDEC standard SSTU32864
Differential Clock inputs
SSTL_18 Clock and data input signaling
Output circuitry minimizes effects of SSO
and unterminated lines
LVCMOS input levels on control and RESET pins
1.7V-1.9V Supply voltage range.
Max Clock frequency > 300MHz
General Description
The SLGSSTU32864 is a configurable registered buffer designed for 1.7V to 1.9V VDD operating range.
When C1 input pin is low, the SLGSSTU32864 is 1:1 25-bit configuration. When C1 input pin is high, the
SLGSSTU32864 is 1:2 14-bit configuration. Additionally, C0 input pin controls the 1:2 pinout as register-A
configuration (if low) , and register-B configuration (if high). The C0,C1, and RESET pins are LVCMOS
input levels.The C0,C1 input pins are not intended to be switched dynamically during normal operation.
They should be tied to logic high or low levels to configure the register.
Data propagation from D to Q is controlled by the differential clock (CLK/CLK) and a control signals. The
rising edge of CLK (crossing with CLK falling) is used to register the Data. All inputs are SSTL_18 except
C0,C1, and RESET pins.
The SLGSSTU32864 supports low-power standby operation. Setting RESET pin to a logic “l(fā)ow” disables
(CLK/CLK) receivers, and allows floating inputs to all other receivers as well (D, V
REF
, CLK/CLK). Addi-
tionally, all internal registers are reset, and outputs (Q) are set “l(fā)ow”. RESET input pin must always be
driven to a valid logic state “high” or “l(fā)ow”.
RESET, an LVCMOS asynchronous signal, is also intended for use at the time of power-up. RESET must
be held at a logic “l(fā)ow” level during power up. This ensures defined outputs before a stable CLK/CLK is
supplied.
The SLGSSTU32864 supports low-power active operation as it monitors DCS and CSR inputs. The Qn
outputs will be prevented from changing states when both DCS and CSR inputs are high. The Qn outputs
will be allowed to change state if either one of DCS or CSR inputs is low. If DCS control is not desired,
then CSR input should be held low. In that case, the setup and hold times of DCS is the same as the other
D inputs.
Ordering Information:
Package type
Package suffix
Topside marking
Ordering code
LFBGA-96ball
13.5 X 5.5 mm body
X
SLGSSTU32864EX
SLGSSTU32864EX-TR
(2,000 pcs/tape and reel)
LFBGA-96ball
13.5 X 5.5 mm body
X
SLGSSTU32864EX
SLGSSTU32864EX (2,000
pcs/tray)
1:1 25-bit or 1:2 14-bit configurable registered
buffer
1.8V data registers
PC3200/4300 DDR2 memory modules
Applications:
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