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參數(shù)資料
| 型號(hào)： | SME5421MCZ-333 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 333 MHz, RISC PROCESSOR, XMA |
| 封裝： | 130 X 100 MM, 45 MM HEIGHT MODULE |
| 文件頁(yè)數(shù)： | 1/34頁(yè) |
| 文件大小： | 619K |
| 代理商： | SME5421MCZ-333 |
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DATA SHEET
1
SME5421MCZ-333
SME5421MCZ-360
UltraSPARC-II
i CPU Module
333/360 MHz CPU, 2-MByte E-cache, UPA64S, 66 MHz PCI
FUNCTIONAL DESCRIPTION
The UltraSPARC-IIi CPU Module [1] is a high performance, SPARC V9-compliant, small form-factor proces-
sor module. It interfaces to the UltraSPARC Port Architecture 64-bit Slave (UPA64S) interconnect bus, main
memory, and the primary PCI bus.
The module consists of one UltraSPARC-IIi CPU, one 64K x 18 cache-tag SRAM,
four 256K x 18 cache-data SRAMs, and circuitry for generating clocks for the processor, SRAM, and UPA64S
bus interface. PCI clocks are generated externally.
Module components nominally operate at 3.3 V and 2.6 V. All signal levels at the module interface are
3.3 V-LVTTL compatible, excepting both the differential UPA clock outputs, which operate at 3.3 V-PECL lev-
els, and the PCI-interface signals, which are 3.3 V-PCI compatible. JTAG output signals are 2.6 V LVTTL
compatible.
The SME5421MCZ-333 module runs at a 333 MHz internal CPU frequency; the SME5421MCZ-360 at
360 MHz. The clock synthesizer sets the frequency and division circuitry operates the UPA frequency at one
third of the internal processor-frequency. The module interface uses two high-speed, impedance-controlled
connectors: see Figure 3.
1. The 360 MHz UltraSPARC-II
i CPU Module
is a recent addition to the UltraSPARC-
i series. See
URL: http://www.sun.com/microelectronics/UltraSPARC/ for other UltraSPARC-
i series products.
Features
Benets
High performance UltraSPARC-IIi CPU
15.2 SPECint95 (est.),19.7 SPECfp95 (est.) at 360 MHz, 2 MB
SPARC V9 compliant
Runs applications that conform to the SPARC
V8 or V9 ABI
Implements VIS
Instruction Set
Comprehensive hardware support for 3D graphics, H-261
compression/decompression, and MPEG2 decompression
64-bit wide data bus
Peak bandwidth of up to 475 MB/s (360 MHz CPU)
2MB external cache (E-cache or L2-cache) clocked at
180 MHz (167 MHz for 333 MHz part)
UltraSPARC-II
i CPU Module pipelined E-cache interface
delivers high performance of up to 1.43 GB/s (360 MHz CPU)
Components operate at 3.3V LVTTL and 2.6V LVTTL
Very high bus speeds with power savings that minimize rate of
heat generation
66 MHz PCI bus to rev. 2.1 PCI specication
Integrated interface simplies I/O system design
130 mm x 100 mm x 45 mm (height) form factor
Small-footprint, modular construction
JTAG (IEEE 1149) boundary-scan interface
Board-level testability
System interface through two impedance-controlled
connectors
High-performance and reliable signal integrity
December 1998
805-5004.frm Page 1 Friday, January 22, 1999 4:42 PM
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