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參數資料
| 型號： | SN54ABT853FK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發器 |
| 英文描述： | ABT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CQCC28 |
| 封裝： | CERAMIC, LCC-28 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 226K |
| 代理商： | SN54ABT853FK |
SN54ABT853, SN74ABT853
8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
D ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
D High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D High-Impedance State During Power Up
and Power Down
D Parity-Error Flag With Parity
Generator/Checker
D Latch for Storage of Parity-Error Flag
D Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Package, and Plastic (NT)
and Ceramic (JT) DIPs
description
The ’ABT853 8-bit to 9-bit parity transceivers are
designed for communication between data buses.
When data is transmitted from the A bus to the
B bus, a parity bit is generated. When data is
transmitted from the B bus to the A bus with its
corresponding parity bit, the open-collector
parity-error (ERR) output indicates whether or not
an error in the B data has occurred. The
output-enable (OEA and OEB) inputs can be used
to disable the device so that the buses are
effectively isolated. The ’ABT853 transceivers
provide true data at their outputs.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from
the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the
designer more system diagnostic capability.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Copyright
1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC-
ΙΙB is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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24
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OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
VCC
B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
LE
SN54ABT853 . . . JT OR W PACKAGE
SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
32 1 28 27
12 13
5
6
7
8
9
10
11
25
24
23
22
21
20
19
B3
B4
B5
NC
B6
B7
B8
A3
A4
A5
NC
A6
A7
A8
426
14 15 16 17 18
ERR
CLR
GND
NC
LE
OEB
P
ARITY
A2
A1
OEA
NC
B1
B2
SN54ABT853 . . . FK PACKAGE
(TOP VIEW)
V
CC
NC – No internal connection
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SN54ABT853JT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
| SN54ABT853W | 制造商:TI 制造商全稱:Texas Instruments 功能描述:8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS |
| SN54ABT8543 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS |
| SN54ABT8543FK | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS |
| SN54ABT8543JT | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SCAN TEST DEVICES WITH OCTAL REGISTERED BUS TRANSCEIVERS |
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