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參數資料
| 型號： | SN54AS175BJ |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 鎖存器 |
| 英文描述： | AS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數： | 1/21頁 |
| 文件大小： | 830K |
| 代理商： | SN54AS175BJ |
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207E - APRIL 1982 - REVISED MAY 2002
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D ’ALS174 and ’AS174 Contain Six Flip-Flops
With Single-Rail Outputs
D ’ALS175 and ’AS175B Contain Four
Flip-Flops With Double-Rail Outputs
D Buffered Clock and Direct-Clear Inputs
D Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
D Fully Buffered Outputs for Maximum
Isolation From External Disturbances
(’AS Only)
SN54ALS175 ...J OR W PACKAGE
SN54AS175B ...J PACKAGE
SN74ALS175, SN74AS175B . . . D, N, OR NS PACKAGE
(TOP VIEW)
SN54ALS174 ...J OR W PACKAGE
SN54AS174 ...J PACKAGE
SN74ALS174, SN74AS174 ...D , N, OR NS PACKAGE
(TOP VIEW)
3
2
1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
6D
5D
NC
5Q
4D
1D
2D
NC
2Q
3D
SN54ALS174, SN54AS174 . . . FK PACKAGE
(TOP VIEW)
1Q
CLR
NC
CLK
4Q
6Q
3Q
GND
NC
NC – No internal connection
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
1Q
1D
2D
2Q
3D
3Q
GND
VCC
6Q
6D
5D
5Q
4D
4Q
CLK
32
1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
4Q
4D
NC
3D
3Q
1Q
1D
NC
2D
2Q
SN54ALS175 . . . FK PACKAGE
(TOP VIEW)
1Q
CLR
NC
CLK
3Q
4Q
2Q
GND
NC
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
1Q
1D
2D
2Q
GND
VCC
4Q
4D
3D
3Q
CLK
description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a
direct-clear (CLR) input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low
level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
Copyright
2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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