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參數資料
| 型號： | SN54LS368J |
| 廠商： | Motorola, Inc. |
| 英文描述： | Quad 2-Input NAND Gate; Package: PDIP-14; No of Pins: 14; Container: Rail; Qty per Container: 500 |
| 中文描述： | 三態緩沖器六角 |
| 文件頁數： | 1/5頁 |
| 文件大小： | 148K |
| 代理商： | SN54LS368J |
5-516
FAST AND LS TTL DATA
3-STATE HEX BUFFERS
These devices are high speed hex buffers with 3-state outputs. They are
organized as single 6-bit or 2-bit/4-bit, with inverting or non-inverting data (D)
paths. The outputs are designed to drive 15 TTL Unit Loads or 60 Low Power
Schottky loads when the Enable (E) is LOW.
When the Output Enable (E) is HIGH, the outputs are forced to a high
impedance “off” state. If the outputs of the 3-state devices are tied together,
all but one device must be in the high impedance state to avoid high currents
that would exceed the maximum ratings. Designers should ensure that Output
Enable signals to 3-state devices whose outputs are tied together are
designed so there is no overlap.
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
–55
0
25
25
125
70
°
C
IOH
Output Current — High
54
74
–1.0
–2.6
mA
IOL
Output Current — Low
54
74
12
24
mA
SN54/74LS365A
SN54/74LS366A
SN54/74LS367A
SN54/74LS368A
3-STATE HEX BUFFERS
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
16
1
D SUFFIX
SOIC
CASE 751B-03
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