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參數(shù)資料
| 型號(hào)： | SN54LS76J |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Serial or Parallel-Input/Serial Output Shift Register; Package: SOIC 16 LEAD; No of Pins: 16; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | 雙JK觸發(fā)器與設(shè)置和清除 |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 63K |
| 代理商： | SN54LS76J |
5-79
FAST AND LS TTL DATA
DUAL JK FLIP-FLOP
WITH SET AND CLEAR
The SN54/74LS76A offers individual J, K, Clock Pulse, Direct Set and Di-
rect Clear inputs. These dual flip-flops are designed so that when the clock
goes HIGH, the inputs are enabled and data will be accepted. The Logic Level
of the J and K inputs will perform according to the Truth Table as long as mini-
mum set-up times are observed. Input data is transferred to the outputs on the
HIGH-to-LOW clock transitions.
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS
OUTPUTS
SD
L
H
L
H
H
H
H
CD
H
L
L
H
H
H
H
J
K
Q
Q
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
X
X
X
h
l
h
l
X
X
X
h
h
l
l
H
L
H
q
L
H
q
L
H
H
q
H
L
q
*Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable
if SD and CD go HIGH simultaneously.
H,h = HIGH Voltage Level
L,l = LOW Voltage Level
X = Immaterial
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one setup time prior
to the HIGH-to-LOW clock transition
LOGIC DIAGRAM
Q
CLEAR (CD)
J
CLOCK (CP)
K
SET (SD)
Q
SN54/74LS76A
DUAL JK FLIP-FLOP
WITH SET AND CLEAR
LOW POWER SCHOTTKY
LOGIC SYMBOL
16
1
4
15
14
K
Q
CP
J
Q
SD
VCC = PIN 5
GND = PIN 13
12
6
9
11
10
K
Q
CP
J
Q
CD
7
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
2
3
8
CD
SD
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