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參數(shù)資料
型號(hào): SN54LS93J
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Single Inverter; Package: SC-88A, SOT-353, SC-70 5 LEAD; No of Pins: 5; Container: Tape and Reel; Qty per Container: 3000
中文描述: LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 3-BIT UP BINARY COUNTER, CDIP14
封裝: CERAMIC, DIP-14
文件頁數(shù): 1/6頁
文件大小: 80K
代理商: SN54LS93J
5-1
FAST AND LS TTL DATA
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di-
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
Low Power Consumption . . . Typically 45 mW
High Count Rates . . . Typically 42 MHz
Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary
Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
LOADING
(Note a)
HIGH
LOW
CP0
Clock (Active LOW going edge) Input to
÷
2 Section
Clock (Active LOW going edge) Input to
÷
5 Section (LS90),
÷
6 Section (LS92)
Clock (Active LOW going edge) Input to
÷
8 Section (LS93)
Master Reset (Clear) Inputs
Master Set (Preset-9, LS90) Inputs
Output from
÷
2 Section (Notes b & c)
Outputs from
÷
5 (LS90),
÷
6 (LS92),
÷
8 (LS93) Sections (Note b)
0.5 U.L.
1.5 U.L.
CP1
0.5 U.L.
2.0 U.L.
CP1
0.5 U.L.
1.0 U.L.
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
μ
A HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b.
Temperature Ranges.
c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
SN54/74LS90
SN54/74LS92
SN54/74LS93
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
14
1
D SUFFIX
SOIC
CASE 751A-02
LOGIC SYMBOL
1 2
2
VCC = PIN 5
GND = PIN 10
NC = PINS 4, 13
VCC = PIN 5
GND = PIN 10
NC = PINS 2, 3, 4, 13
VCC = PIN 5
GND = PIN 10
NC = PIN 4, 6, 7, 13
LS90
LS92
LS93
6 7
1 2
14
1
1 2
2 3
MS
CP0
CP1
MR Q0Q1Q2Q3
12 9
8 11
6 7
14
1
1
CP0
CP1
MR Q0Q1Q2Q3
12
9
8
11
14
1
2 3
CP0
CP1
MR Q0Q1Q2Q3
12 9
8 11
相關(guān)PDF資料
PDF描述
SN74LS92D Silicon Controlled Rectifier; Package: TO-220 3 LEAD STANDARD; No of Pins: 3; Container: Rail; Qty per Container: 50
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SN74LS93D DECADE COUNTER; DIVIDE-BY-TWELVE COUNTER; 4-BIT BINARY COUNTER
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