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參數(shù)資料
| 型號(hào)： | SN54LV165J |
| 廠(chǎng)商： | Texas Instruments, Inc. |
| 英文描述： | Octal Inverting Buffer/Line Driver/Line Receiver, 3 State; Package: TSSOP 20 LEAD; No of Pins: 20; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | 并行-載重8位轉(zhuǎn)換寄存器 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大小： | 168K |
| 代理商： | SN54LV165J |
SN54LV165, SN74LV165
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCES007B – MARCH 1995 – REVISED APRIL 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
EPIC
(Enhanced-Performance Implanted
CMOS) 2-
μ
Process
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
, T
A
= 25
°
C
Typical V
OHV
(Output V
OH
Undershoot)
< 2 V at V
CC
, T
A
= 25
°
C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
description
The ’LV165 parallel-load, 8-bit shift registers are
designed for 2.7-V to 5.5-V V
CC
operation.
When the device is clocked, data is shifted toward
the serial output Q
H
. Parallel-in access to each
stage is provided by eight individual direct data
inputs that are enabled by a low level at the SH/LD
input. The ’LV165 feature a clock inhibit function
and a complemented serial output Q
H
.
Clocking is accomplished by a low-to-high
transition of the clock (CLK) input while SH/LD is
held high and clock inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are
interchangeable. Since a low CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK
INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held
high. The parallel inputs to the register are enabled while SH/LD is held low independently of the levels of CLK,
CLK INH, or SER.
The SN54LV165 is characterized for operation over the full military temperature range of –55
°
C to 125
°
C. The
SN74LV165 is characterized for operation from –40
°
C to 85
°
C.
FUNCTION TABLE
INPUTS
OPERATION
SH/LD
L
CLK
X
CLK INH
X
Parallel load
H
H
X
Q0
Q0
Shift
H
X
H
↑
L
H
L
↑
H
Shift
Copyright
1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
EPIC is a trademark of Texas Instruments Incorporated.
SN54LV165 . . . J OR W PACKAGE
SN74LV165 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
D
C
NC
B
A
E
F
NC
G
H
SN54LV165 . . . FK PACKAGE
(TOP VIEW)
C
S
N
S
C
Q
G
N
V
C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SH/LD
CLK
E
F
G
H
Q
H
GND
V
CC
CLK INH
D
C
B
A
SER
Q
H
Q
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54LV165W | Octal Inverting Buffer/Line Driver/Line Receiver, 3 State; Package: SOIC-20 WB; No of Pins: 20; Container: Rail; Qty per Container: 38 |
| SN74LV165PW | PARALLEL-LOAD 8-BIT SHIFT REGISTERS |
| SN74LV175ADBR | QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
| SN74LV175ADBRE4 | QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
| SN74LV175V | QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
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