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參數資料
| 型號： | SN54LVTH182512HKC |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發器 |
| 英文描述： | LVT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CDFP64 |
| 封裝： | 0.50 MM PITCH, CERAMIC, FP-64 |
| 文件頁數： | 1/34頁 |
| 文件大小： | 518K |
| 代理商： | SN54LVTH182512HKC |
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SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997
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POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Members of the Texas Instruments
SCOPE
Family of Testability Products
D Members of the Texas Instruments
Widebus
Family
D State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V VCC)
D Support Unregulated Battery Operation
Down to 2.7 V
D UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D B-Port Outputs of ’LVTH182512 Devices
Have Equivalent 25-
Series Resistors, So
No External Resistors Are Required
D Compatible With the IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture
D SCOPE Instruction Set
– IEEE Std 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
D Package Options Include 64-Pin Plastic
Thin Shrink Small Outline (DGG) and 64-Pin
Ceramic Dual Flat (HKC) Packages Using
0.5-mm Center-to-Center Spacings
description
The ’LVTH18512 and ’LVTH182512 scan test devices with 18-bit universal bus transceivers are members of
the Texas Instruments SCOPE
testability integrated-circuit family. This family of devices supports IEEE Std
1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test
circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
Copyright
1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.
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1CLKAB
1LEAB
1OEAB
1A1
1A2
GND
1A3
1A4
1A5
VCC
1A6
1A7
1A8
GND
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
2A9
GND
2OEAB
2LEAB
2CLKAB
TDO
TMS
1CLKBA
1LEBA
1OEBA
1B1
1B2
GND
1B3
1B4
1B5
VCC
1B6
1B7
1B8
GND
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
2B9
GND
2OEBA
2LEBA
2CLKBA
TDI
TCK
SN54LVTH18512, SN54LVTH182512 . . . HKC PACKAGE
SN74LVTH18512, SN74LVTH182512 . . . DGG PACKAGE
(TOP VIEW)
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