- 您現在的位置：買賣IC網 > PDF目錄98089 > SN54LVTH573FK (TEXAS INSTRUMENTS INC) LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20 PDF資料下載
參數資料
| 型號： | SN54LVTH573FK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線收發器 |
| 英文描述： | LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 201K |
| 代理商： | SN54LVTH573FK |
SN54LVTH573, SN74LVTH573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS687F – MAY 1997 – REVISED JULY 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
D Support Unregulated Battery Operation
Down to 2.7 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Ioff and Power-Up 3-State Support Hot
Insertion
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
description
These octal latches are designed specifically for
low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V
system environment.
The eight latches of the ’LVTH573 devices are
transparent
D-type
latches.
While
the
latch-enable (LE) input is high, the Q outputs
follow the data (D) inputs. When LE is taken low,
the Q outputs are latched at the logic levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
Copyright
2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54LVTH573 ...J OR W PACKAGE
SN74LVTH573 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
SN54LVTH573 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
32 1 20 19
910 11 12 13
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q
1Q
8D
GND
LE
V
CC
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
相關PDF資料 |
PDF描述 |
|---|---|
| SN54LVTH646JT | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDIP24 |
| SN54LVTH652FK | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CQCC28 |
| SN74LVTH652DGV | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| SN54S112AW | S SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16 |
| SN54S163W | S SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDFP16 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SN54S00J | 制造商:Texas Instruments 功能描述:NAND Gate 4-Element 2-IN Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S00W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| SN54S02J | 制造商:Texas Instruments 功能描述: |
| SN54S03J | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:2-INPUT NAND GATE (OC) - Rail/Tube |
| SN54S04J | 制造商:Texas Instruments 功能描述:Inverter 6-Element Bipolar 14-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:INVERTER 6-ELEM BIPOLAR 14CDIP - Rail/Tube 制造商:Texas Instruments 功能描述:HEX INVERTER *NIC* |
發布緊急采購，3分鐘左右您將得到回復。