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參數資料
型號: SN74ALVC162835DL
廠商: TEXAS INSTRUMENTS INC
元件分類: 總線收發器
英文描述: ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56
封裝: GREEN, PLASTIC, SSOP-56
文件頁數: 1/14頁
文件大小: 395K
代理商: SN74ALVC162835DL
www.ti.com
FEATURES
DESCRIPTION/ORDERING INFORMATION
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NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
NC No internal connection
SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES126H – FEBRUARY 1998 – REVISED SEPTEMBER 2004
Member of the Texas Instruments Widebus
Family
Operates From 1.65 V to 3.6 V
Max tpd of 2 ns at 3.3 V
±12-mA Output Drive at 3.3 V
Ideal for Use in PC100 Register DIMM,
Revision 1.1
Output Port Has Equivalent 26-
Series
Resistors, So No External Resistors Are
Required
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
This 18-bit universal bus driver is designed for 1.65-V
to 3.6-V VCC operation.
Data
flow
from
A
to
Y
is
controlled
by
the
output-enable (OE) input. The device operates in the
transparent mode when the latch-enable (LE) input is
high. When LE is low, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If
LE is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When OE is high,
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
The output port includes equivalent 26-
series
resistors to reduce overshoot and undershoot.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
Tube
SN74ALVC162835DL
SSOP - DL
ALVC162835
Tape and reel
SN74ALVC162835DLR
-40
°C to 85°C
TSSOP - DGG
Tape and reel
SN74ALVC162835DGGR
ALVC162835
TVSOP - DGV
Tape and reel
SN74ALVC162835DGVR
VC2835
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 1998–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
相關PDF資料
PDF描述
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相關代理商/技術參數
參數描述
SN74ALVC162835DLR 功能描述:總線收發器 18B Universal Bus Driver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVC162836DGGR 功能描述:通用總線函數 20bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數量:1 開啟電阻(最大值): 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVC162836DGVR 功能描述:通用總線函數 20bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數量:1 開啟電阻(最大值): 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVC162836DL 功能描述:通用總線函數 20bit Univ Bus RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數量:1 開啟電阻(最大值): 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel
SN74ALVC162836DLR 功能描述:總線收發器 20B Universal Bus Driver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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